758 lines
25 KiB
C++
758 lines
25 KiB
C++
// Copyright 2015, ARM Limited
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// * Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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// * Redistributions in binary form must reproduce the above copyright notice,
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// this list of conditions and the following disclaimer in the documentation
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// and/or other materials provided with the distribution.
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// * Neither the name of ARM Limited nor the names of its contributors may be
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// used to endorse or promote products derived from this software without
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// specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE
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// FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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// DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
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// SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
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// CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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// OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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#ifndef VIXL_A64_INSTRUCTIONS_A64_H_
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#define VIXL_A64_INSTRUCTIONS_A64_H_
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#include "vixl/globals.h"
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#include "vixl/utils.h"
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#include "vixl/a64/constants-a64.h"
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namespace vixl {
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// ISA constants. --------------------------------------------------------------
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typedef uint32_t Instr;
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const unsigned kInstructionSize = 4;
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const unsigned kInstructionSizeLog2 = 2;
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const unsigned kLiteralEntrySize = 4;
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const unsigned kLiteralEntrySizeLog2 = 2;
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const unsigned kMaxLoadLiteralRange = 1 * MBytes;
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// This is the nominal page size (as used by the adrp instruction); the actual
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// size of the memory pages allocated by the kernel is likely to differ.
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const unsigned kPageSize = 4 * KBytes;
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const unsigned kPageSizeLog2 = 12;
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const unsigned kBRegSize = 8;
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const unsigned kBRegSizeLog2 = 3;
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const unsigned kBRegSizeInBytes = kBRegSize / 8;
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const unsigned kBRegSizeInBytesLog2 = kBRegSizeLog2 - 3;
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const unsigned kHRegSize = 16;
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const unsigned kHRegSizeLog2 = 4;
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const unsigned kHRegSizeInBytes = kHRegSize / 8;
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const unsigned kHRegSizeInBytesLog2 = kHRegSizeLog2 - 3;
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const unsigned kWRegSize = 32;
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const unsigned kWRegSizeLog2 = 5;
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const unsigned kWRegSizeInBytes = kWRegSize / 8;
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const unsigned kWRegSizeInBytesLog2 = kWRegSizeLog2 - 3;
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const unsigned kXRegSize = 64;
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const unsigned kXRegSizeLog2 = 6;
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const unsigned kXRegSizeInBytes = kXRegSize / 8;
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const unsigned kXRegSizeInBytesLog2 = kXRegSizeLog2 - 3;
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const unsigned kSRegSize = 32;
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const unsigned kSRegSizeLog2 = 5;
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const unsigned kSRegSizeInBytes = kSRegSize / 8;
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const unsigned kSRegSizeInBytesLog2 = kSRegSizeLog2 - 3;
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const unsigned kDRegSize = 64;
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const unsigned kDRegSizeLog2 = 6;
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const unsigned kDRegSizeInBytes = kDRegSize / 8;
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const unsigned kDRegSizeInBytesLog2 = kDRegSizeLog2 - 3;
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const unsigned kQRegSize = 128;
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const unsigned kQRegSizeLog2 = 7;
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const unsigned kQRegSizeInBytes = kQRegSize / 8;
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const unsigned kQRegSizeInBytesLog2 = kQRegSizeLog2 - 3;
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const uint64_t kWRegMask = UINT64_C(0xffffffff);
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const uint64_t kXRegMask = UINT64_C(0xffffffffffffffff);
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const uint64_t kSRegMask = UINT64_C(0xffffffff);
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const uint64_t kDRegMask = UINT64_C(0xffffffffffffffff);
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const uint64_t kSSignMask = UINT64_C(0x80000000);
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const uint64_t kDSignMask = UINT64_C(0x8000000000000000);
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const uint64_t kWSignMask = UINT64_C(0x80000000);
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const uint64_t kXSignMask = UINT64_C(0x8000000000000000);
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const uint64_t kByteMask = UINT64_C(0xff);
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const uint64_t kHalfWordMask = UINT64_C(0xffff);
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const uint64_t kWordMask = UINT64_C(0xffffffff);
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const uint64_t kXMaxUInt = UINT64_C(0xffffffffffffffff);
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const uint64_t kWMaxUInt = UINT64_C(0xffffffff);
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const int64_t kXMaxInt = INT64_C(0x7fffffffffffffff);
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const int64_t kXMinInt = INT64_C(0x8000000000000000);
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const int32_t kWMaxInt = INT32_C(0x7fffffff);
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const int32_t kWMinInt = INT32_C(0x80000000);
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const unsigned kLinkRegCode = 30;
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const unsigned kZeroRegCode = 31;
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const unsigned kSPRegInternalCode = 63;
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const unsigned kRegCodeMask = 0x1f;
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const unsigned kAddressTagOffset = 56;
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const unsigned kAddressTagWidth = 8;
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const uint64_t kAddressTagMask =
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((UINT64_C(1) << kAddressTagWidth) - 1) << kAddressTagOffset;
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VIXL_STATIC_ASSERT(kAddressTagMask == UINT64_C(0xff00000000000000));
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// AArch64 floating-point specifics. These match IEEE-754.
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const unsigned kDoubleMantissaBits = 52;
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const unsigned kDoubleExponentBits = 11;
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const unsigned kFloatMantissaBits = 23;
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const unsigned kFloatExponentBits = 8;
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const unsigned kFloat16MantissaBits = 10;
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const unsigned kFloat16ExponentBits = 5;
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// Floating-point infinity values.
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extern const float16 kFP16PositiveInfinity;
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extern const float16 kFP16NegativeInfinity;
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extern const float kFP32PositiveInfinity;
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extern const float kFP32NegativeInfinity;
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extern const double kFP64PositiveInfinity;
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extern const double kFP64NegativeInfinity;
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// The default NaN values (for FPCR.DN=1).
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extern const float16 kFP16DefaultNaN;
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extern const float kFP32DefaultNaN;
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extern const double kFP64DefaultNaN;
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unsigned CalcLSDataSize(LoadStoreOp op);
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unsigned CalcLSPairDataSize(LoadStorePairOp op);
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enum ImmBranchType {
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UnknownBranchType = 0,
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CondBranchType = 1,
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UncondBranchType = 2,
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CompareBranchType = 3,
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TestBranchType = 4
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};
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enum AddrMode {
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Offset,
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PreIndex,
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PostIndex
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};
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enum FPRounding {
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// The first four values are encodable directly by FPCR<RMode>.
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FPTieEven = 0x0,
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FPPositiveInfinity = 0x1,
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FPNegativeInfinity = 0x2,
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FPZero = 0x3,
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// The final rounding modes are only available when explicitly specified by
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// the instruction (such as with fcvta). It cannot be set in FPCR.
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FPTieAway,
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FPRoundOdd
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};
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enum Reg31Mode {
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Reg31IsStackPointer,
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Reg31IsZeroRegister
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};
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// Instructions. ---------------------------------------------------------------
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class Instruction {
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public:
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Instr InstructionBits() const {
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return *(reinterpret_cast<const Instr*>(this));
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}
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void SetInstructionBits(Instr new_instr) {
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*(reinterpret_cast<Instr*>(this)) = new_instr;
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}
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int Bit(int pos) const {
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return (InstructionBits() >> pos) & 1;
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}
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uint32_t Bits(int msb, int lsb) const {
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return unsigned_bitextract_32(msb, lsb, InstructionBits());
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}
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int32_t SignedBits(int msb, int lsb) const {
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int32_t bits = *(reinterpret_cast<const int32_t*>(this));
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return signed_bitextract_32(msb, lsb, bits);
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}
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Instr Mask(uint32_t mask) const {
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return InstructionBits() & mask;
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}
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#define DEFINE_GETTER(Name, HighBit, LowBit, Func) \
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int32_t Name() const { return Func(HighBit, LowBit); }
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INSTRUCTION_FIELDS_LIST(DEFINE_GETTER)
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#undef DEFINE_GETTER
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// ImmPCRel is a compound field (not present in INSTRUCTION_FIELDS_LIST),
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// formed from ImmPCRelLo and ImmPCRelHi.
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int ImmPCRel() const {
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int offset =
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static_cast<int>((ImmPCRelHi() << ImmPCRelLo_width) | ImmPCRelLo());
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int width = ImmPCRelLo_width + ImmPCRelHi_width;
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return signed_bitextract_32(width - 1, 0, offset);
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}
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uint64_t ImmLogical() const;
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unsigned ImmNEONabcdefgh() const;
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float ImmFP32() const;
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double ImmFP64() const;
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float ImmNEONFP32() const;
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double ImmNEONFP64() const;
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unsigned SizeLS() const {
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return CalcLSDataSize(static_cast<LoadStoreOp>(Mask(LoadStoreMask)));
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}
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unsigned SizeLSPair() const {
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return CalcLSPairDataSize(
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static_cast<LoadStorePairOp>(Mask(LoadStorePairMask)));
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}
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int NEONLSIndex(int access_size_shift) const {
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int64_t q = NEONQ();
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int64_t s = NEONS();
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int64_t size = NEONLSSize();
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int64_t index = (q << 3) | (s << 2) | size;
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return static_cast<int>(index >> access_size_shift);
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}
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// Helpers.
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bool IsCondBranchImm() const {
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return Mask(ConditionalBranchFMask) == ConditionalBranchFixed;
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}
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bool IsUncondBranchImm() const {
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return Mask(UnconditionalBranchFMask) == UnconditionalBranchFixed;
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}
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bool IsCompareBranch() const {
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return Mask(CompareBranchFMask) == CompareBranchFixed;
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}
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bool IsTestBranch() const {
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return Mask(TestBranchFMask) == TestBranchFixed;
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}
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bool IsImmBranch() const {
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return BranchType() != UnknownBranchType;
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}
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bool IsPCRelAddressing() const {
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return Mask(PCRelAddressingFMask) == PCRelAddressingFixed;
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}
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bool IsLogicalImmediate() const {
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return Mask(LogicalImmediateFMask) == LogicalImmediateFixed;
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}
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bool IsAddSubImmediate() const {
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return Mask(AddSubImmediateFMask) == AddSubImmediateFixed;
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}
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bool IsAddSubExtended() const {
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return Mask(AddSubExtendedFMask) == AddSubExtendedFixed;
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}
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bool IsLoadOrStore() const {
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return Mask(LoadStoreAnyFMask) == LoadStoreAnyFixed;
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}
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bool IsLoad() const;
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bool IsStore() const;
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bool IsLoadLiteral() const {
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// This includes PRFM_lit.
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return Mask(LoadLiteralFMask) == LoadLiteralFixed;
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}
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bool IsMovn() const {
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return (Mask(MoveWideImmediateMask) == MOVN_x) ||
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(Mask(MoveWideImmediateMask) == MOVN_w);
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}
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static int ImmBranchRangeBitwidth(ImmBranchType branch_type);
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static int32_t ImmBranchForwardRange(ImmBranchType branch_type);
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static bool IsValidImmPCOffset(ImmBranchType branch_type, int64_t offset);
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// Indicate whether Rd can be the stack pointer or the zero register. This
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// does not check that the instruction actually has an Rd field.
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Reg31Mode RdMode() const {
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// The following instructions use sp or wsp as Rd:
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// Add/sub (immediate) when not setting the flags.
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// Add/sub (extended) when not setting the flags.
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// Logical (immediate) when not setting the flags.
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// Otherwise, r31 is the zero register.
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if (IsAddSubImmediate() || IsAddSubExtended()) {
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if (Mask(AddSubSetFlagsBit)) {
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return Reg31IsZeroRegister;
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} else {
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return Reg31IsStackPointer;
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}
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}
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if (IsLogicalImmediate()) {
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// Of the logical (immediate) instructions, only ANDS (and its aliases)
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// can set the flags. The others can all write into sp.
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// Note that some logical operations are not available to
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// immediate-operand instructions, so we have to combine two masks here.
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if (Mask(LogicalImmediateMask & LogicalOpMask) == ANDS) {
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return Reg31IsZeroRegister;
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} else {
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return Reg31IsStackPointer;
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}
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}
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return Reg31IsZeroRegister;
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}
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// Indicate whether Rn can be the stack pointer or the zero register. This
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// does not check that the instruction actually has an Rn field.
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Reg31Mode RnMode() const {
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// The following instructions use sp or wsp as Rn:
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// All loads and stores.
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// Add/sub (immediate).
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// Add/sub (extended).
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// Otherwise, r31 is the zero register.
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if (IsLoadOrStore() || IsAddSubImmediate() || IsAddSubExtended()) {
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return Reg31IsStackPointer;
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}
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return Reg31IsZeroRegister;
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}
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ImmBranchType BranchType() const {
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if (IsCondBranchImm()) {
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return CondBranchType;
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} else if (IsUncondBranchImm()) {
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return UncondBranchType;
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} else if (IsCompareBranch()) {
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return CompareBranchType;
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} else if (IsTestBranch()) {
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return TestBranchType;
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} else {
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return UnknownBranchType;
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}
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}
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// Find the target of this instruction. 'this' may be a branch or a
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// PC-relative addressing instruction.
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const Instruction* ImmPCOffsetTarget() const;
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// Patch a PC-relative offset to refer to 'target'. 'this' may be a branch or
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// a PC-relative addressing instruction.
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void SetImmPCOffsetTarget(const Instruction* target);
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// Patch a literal load instruction to load from 'source'.
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void SetImmLLiteral(const Instruction* source);
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// The range of a load literal instruction, expressed as 'instr +- range'.
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// The range is actually the 'positive' range; the branch instruction can
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// target [instr - range - kInstructionSize, instr + range].
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static const int kLoadLiteralImmBitwidth = 19;
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static const int kLoadLiteralRange =
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(1 << kLoadLiteralImmBitwidth) / 2 - kInstructionSize;
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// Calculate the address of a literal referred to by a load-literal
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// instruction, and return it as the specified type.
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//
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// The literal itself is safely mutable only if the backing buffer is safely
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// mutable.
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template <typename T>
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T LiteralAddress() const {
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uint64_t base_raw = reinterpret_cast<uint64_t>(this);
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int64_t offset = ImmLLiteral() << kLiteralEntrySizeLog2;
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uint64_t address_raw = base_raw + offset;
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// Cast the address using a C-style cast. A reinterpret_cast would be
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// appropriate, but it can't cast one integral type to another.
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T address = (T)(address_raw);
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// Assert that the address can be represented by the specified type.
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VIXL_ASSERT((uint64_t)(address) == address_raw);
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return address;
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}
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uint32_t Literal32() const {
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uint32_t literal;
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memcpy(&literal, LiteralAddress<const void*>(), sizeof(literal));
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return literal;
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}
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uint64_t Literal64() const {
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uint64_t literal;
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memcpy(&literal, LiteralAddress<const void*>(), sizeof(literal));
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return literal;
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}
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float LiteralFP32() const {
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return rawbits_to_float(Literal32());
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}
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double LiteralFP64() const {
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return rawbits_to_double(Literal64());
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}
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const Instruction* NextInstruction() const {
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return this + kInstructionSize;
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}
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const Instruction* InstructionAtOffset(int64_t offset) const {
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VIXL_ASSERT(IsWordAligned(this + offset));
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return this + offset;
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}
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template<typename T> static Instruction* Cast(T src) {
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return reinterpret_cast<Instruction*>(src);
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}
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template<typename T> static const Instruction* CastConst(T src) {
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return reinterpret_cast<const Instruction*>(src);
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}
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private:
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int ImmBranch() const;
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static float Imm8ToFP32(uint32_t imm8);
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static double Imm8ToFP64(uint32_t imm8);
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void SetPCRelImmTarget(const Instruction* target);
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void SetBranchImmTarget(const Instruction* target);
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};
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// Functions for handling NEON vector format information.
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enum VectorFormat {
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kFormatUndefined = 0xffffffff,
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kFormat8B = NEON_8B,
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kFormat16B = NEON_16B,
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kFormat4H = NEON_4H,
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kFormat8H = NEON_8H,
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kFormat2S = NEON_2S,
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kFormat4S = NEON_4S,
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kFormat1D = NEON_1D,
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kFormat2D = NEON_2D,
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// Scalar formats. We add the scalar bit to distinguish between scalar and
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// vector enumerations; the bit is always set in the encoding of scalar ops
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// and always clear for vector ops. Although kFormatD and kFormat1D appear
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// to be the same, their meaning is subtly different. The first is a scalar
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// operation, the second a vector operation that only affects one lane.
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kFormatB = NEON_B | NEONScalar,
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kFormatH = NEON_H | NEONScalar,
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kFormatS = NEON_S | NEONScalar,
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kFormatD = NEON_D | NEONScalar
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};
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VectorFormat VectorFormatHalfWidth(const VectorFormat vform);
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VectorFormat VectorFormatDoubleWidth(const VectorFormat vform);
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VectorFormat VectorFormatDoubleLanes(const VectorFormat vform);
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VectorFormat VectorFormatHalfLanes(const VectorFormat vform);
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VectorFormat ScalarFormatFromLaneSize(int lanesize);
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VectorFormat VectorFormatHalfWidthDoubleLanes(const VectorFormat vform);
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VectorFormat VectorFormatFillQ(const VectorFormat vform);
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unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
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unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
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// TODO: Make the return types of these functions consistent.
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unsigned LaneSizeInBitsFromFormat(VectorFormat vform);
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int LaneSizeInBytesFromFormat(VectorFormat vform);
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int LaneSizeInBytesLog2FromFormat(VectorFormat vform);
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int LaneCountFromFormat(VectorFormat vform);
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int MaxLaneCountFromFormat(VectorFormat vform);
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bool IsVectorFormat(VectorFormat vform);
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int64_t MaxIntFromFormat(VectorFormat vform);
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int64_t MinIntFromFormat(VectorFormat vform);
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uint64_t MaxUintFromFormat(VectorFormat vform);
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enum NEONFormat {
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NF_UNDEF = 0,
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NF_8B = 1,
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NF_16B = 2,
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NF_4H = 3,
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NF_8H = 4,
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NF_2S = 5,
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NF_4S = 6,
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NF_1D = 7,
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NF_2D = 8,
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NF_B = 9,
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NF_H = 10,
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NF_S = 11,
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NF_D = 12
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};
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static const unsigned kNEONFormatMaxBits = 6;
|
|
|
|
struct NEONFormatMap {
|
|
// The bit positions in the instruction to consider.
|
|
uint8_t bits[kNEONFormatMaxBits];
|
|
|
|
// Mapping from concatenated bits to format.
|
|
NEONFormat map[1 << kNEONFormatMaxBits];
|
|
};
|
|
|
|
class NEONFormatDecoder {
|
|
public:
|
|
enum SubstitutionMode {
|
|
kPlaceholder,
|
|
kFormat
|
|
};
|
|
|
|
// Construct a format decoder with increasingly specific format maps for each
|
|
// subsitution. If no format map is specified, the default is the integer
|
|
// format map.
|
|
explicit NEONFormatDecoder(const Instruction* instr) {
|
|
instrbits_ = instr->InstructionBits();
|
|
SetFormatMaps(IntegerFormatMap());
|
|
}
|
|
NEONFormatDecoder(const Instruction* instr,
|
|
const NEONFormatMap* format) {
|
|
instrbits_ = instr->InstructionBits();
|
|
SetFormatMaps(format);
|
|
}
|
|
NEONFormatDecoder(const Instruction* instr,
|
|
const NEONFormatMap* format0,
|
|
const NEONFormatMap* format1) {
|
|
instrbits_ = instr->InstructionBits();
|
|
SetFormatMaps(format0, format1);
|
|
}
|
|
NEONFormatDecoder(const Instruction* instr,
|
|
const NEONFormatMap* format0,
|
|
const NEONFormatMap* format1,
|
|
const NEONFormatMap* format2) {
|
|
instrbits_ = instr->InstructionBits();
|
|
SetFormatMaps(format0, format1, format2);
|
|
}
|
|
|
|
// Set the format mapping for all or individual substitutions.
|
|
void SetFormatMaps(const NEONFormatMap* format0,
|
|
const NEONFormatMap* format1 = NULL,
|
|
const NEONFormatMap* format2 = NULL) {
|
|
VIXL_ASSERT(format0 != NULL);
|
|
formats_[0] = format0;
|
|
formats_[1] = (format1 == NULL) ? formats_[0] : format1;
|
|
formats_[2] = (format2 == NULL) ? formats_[1] : format2;
|
|
}
|
|
void SetFormatMap(unsigned index, const NEONFormatMap* format) {
|
|
VIXL_ASSERT(index <= (sizeof(formats_) / sizeof(formats_[0])));
|
|
VIXL_ASSERT(format != NULL);
|
|
formats_[index] = format;
|
|
}
|
|
|
|
// Substitute %s in the input string with the placeholder string for each
|
|
// register, ie. "'B", "'H", etc.
|
|
const char* SubstitutePlaceholders(const char* string) {
|
|
return Substitute(string, kPlaceholder, kPlaceholder, kPlaceholder);
|
|
}
|
|
|
|
// Substitute %s in the input string with a new string based on the
|
|
// substitution mode.
|
|
const char* Substitute(const char* string,
|
|
SubstitutionMode mode0 = kFormat,
|
|
SubstitutionMode mode1 = kFormat,
|
|
SubstitutionMode mode2 = kFormat) {
|
|
snprintf(form_buffer_, sizeof(form_buffer_), string,
|
|
GetSubstitute(0, mode0),
|
|
GetSubstitute(1, mode1),
|
|
GetSubstitute(2, mode2));
|
|
return form_buffer_;
|
|
}
|
|
|
|
// Append a "2" to a mnemonic string based of the state of the Q bit.
|
|
const char* Mnemonic(const char* mnemonic) {
|
|
if ((instrbits_ & NEON_Q) != 0) {
|
|
snprintf(mne_buffer_, sizeof(mne_buffer_), "%s2", mnemonic);
|
|
return mne_buffer_;
|
|
}
|
|
return mnemonic;
|
|
}
|
|
|
|
VectorFormat GetVectorFormat(int format_index = 0) {
|
|
return GetVectorFormat(formats_[format_index]);
|
|
}
|
|
|
|
VectorFormat GetVectorFormat(const NEONFormatMap* format_map) {
|
|
static const VectorFormat vform[] = {
|
|
kFormatUndefined,
|
|
kFormat8B, kFormat16B, kFormat4H, kFormat8H,
|
|
kFormat2S, kFormat4S, kFormat1D, kFormat2D,
|
|
kFormatB, kFormatH, kFormatS, kFormatD
|
|
};
|
|
VIXL_ASSERT(GetNEONFormat(format_map) < (sizeof(vform) / sizeof(vform[0])));
|
|
return vform[GetNEONFormat(format_map)];
|
|
}
|
|
|
|
// Built in mappings for common cases.
|
|
|
|
// The integer format map uses three bits (Q, size<1:0>) to encode the
|
|
// "standard" set of NEON integer vector formats.
|
|
static const NEONFormatMap* IntegerFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{23, 22, 30},
|
|
{NF_8B, NF_16B, NF_4H, NF_8H, NF_2S, NF_4S, NF_UNDEF, NF_2D}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The long integer format map uses two bits (size<1:0>) to encode the
|
|
// long set of NEON integer vector formats. These are used in narrow, wide
|
|
// and long operations.
|
|
static const NEONFormatMap* LongIntegerFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{23, 22}, {NF_8H, NF_4S, NF_2D}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The FP format map uses two bits (Q, size<0>) to encode the NEON FP vector
|
|
// formats: NF_2S, NF_4S, NF_2D.
|
|
static const NEONFormatMap* FPFormatMap() {
|
|
// The FP format map assumes two bits (Q, size<0>) are used to encode the
|
|
// NEON FP vector formats: NF_2S, NF_4S, NF_2D.
|
|
static const NEONFormatMap map = {
|
|
{22, 30}, {NF_2S, NF_4S, NF_UNDEF, NF_2D}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The load/store format map uses three bits (Q, 11, 10) to encode the
|
|
// set of NEON vector formats.
|
|
static const NEONFormatMap* LoadStoreFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{11, 10, 30},
|
|
{NF_8B, NF_16B, NF_4H, NF_8H, NF_2S, NF_4S, NF_1D, NF_2D}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The logical format map uses one bit (Q) to encode the NEON vector format:
|
|
// NF_8B, NF_16B.
|
|
static const NEONFormatMap* LogicalFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{30}, {NF_8B, NF_16B}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The triangular format map uses between two and five bits to encode the NEON
|
|
// vector format:
|
|
// xxx10->8B, xxx11->16B, xx100->4H, xx101->8H
|
|
// x1000->2S, x1001->4S, 10001->2D, all others undefined.
|
|
static const NEONFormatMap* TriangularFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{19, 18, 17, 16, 30},
|
|
{NF_UNDEF, NF_UNDEF, NF_8B, NF_16B, NF_4H, NF_8H, NF_8B, NF_16B, NF_2S,
|
|
NF_4S, NF_8B, NF_16B, NF_4H, NF_8H, NF_8B, NF_16B, NF_UNDEF, NF_2D,
|
|
NF_8B, NF_16B, NF_4H, NF_8H, NF_8B, NF_16B, NF_2S, NF_4S, NF_8B, NF_16B,
|
|
NF_4H, NF_8H, NF_8B, NF_16B}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The scalar format map uses two bits (size<1:0>) to encode the NEON scalar
|
|
// formats: NF_B, NF_H, NF_S, NF_D.
|
|
static const NEONFormatMap* ScalarFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{23, 22}, {NF_B, NF_H, NF_S, NF_D}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The long scalar format map uses two bits (size<1:0>) to encode the longer
|
|
// NEON scalar formats: NF_H, NF_S, NF_D.
|
|
static const NEONFormatMap* LongScalarFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{23, 22}, {NF_H, NF_S, NF_D}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The FP scalar format map assumes one bit (size<0>) is used to encode the
|
|
// NEON FP scalar formats: NF_S, NF_D.
|
|
static const NEONFormatMap* FPScalarFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{22}, {NF_S, NF_D}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
// The triangular scalar format map uses between one and four bits to encode
|
|
// the NEON FP scalar formats:
|
|
// xxx1->B, xx10->H, x100->S, 1000->D, all others undefined.
|
|
static const NEONFormatMap* TriangularScalarFormatMap() {
|
|
static const NEONFormatMap map = {
|
|
{19, 18, 17, 16},
|
|
{NF_UNDEF, NF_B, NF_H, NF_B, NF_S, NF_B, NF_H, NF_B,
|
|
NF_D, NF_B, NF_H, NF_B, NF_S, NF_B, NF_H, NF_B}
|
|
};
|
|
return ↦
|
|
}
|
|
|
|
private:
|
|
// Get a pointer to a string that represents the format or placeholder for
|
|
// the specified substitution index, based on the format map and instruction.
|
|
const char* GetSubstitute(int index, SubstitutionMode mode) {
|
|
if (mode == kFormat) {
|
|
return NEONFormatAsString(GetNEONFormat(formats_[index]));
|
|
}
|
|
VIXL_ASSERT(mode == kPlaceholder);
|
|
return NEONFormatAsPlaceholder(GetNEONFormat(formats_[index]));
|
|
}
|
|
|
|
// Get the NEONFormat enumerated value for bits obtained from the
|
|
// instruction based on the specified format mapping.
|
|
NEONFormat GetNEONFormat(const NEONFormatMap* format_map) {
|
|
return format_map->map[PickBits(format_map->bits)];
|
|
}
|
|
|
|
// Convert a NEONFormat into a string.
|
|
static const char* NEONFormatAsString(NEONFormat format) {
|
|
static const char* formats[] = {
|
|
"undefined",
|
|
"8b", "16b", "4h", "8h", "2s", "4s", "1d", "2d",
|
|
"b", "h", "s", "d"
|
|
};
|
|
VIXL_ASSERT(format < (sizeof(formats) / sizeof(formats[0])));
|
|
return formats[format];
|
|
}
|
|
|
|
// Convert a NEONFormat into a register placeholder string.
|
|
static const char* NEONFormatAsPlaceholder(NEONFormat format) {
|
|
VIXL_ASSERT((format == NF_B) || (format == NF_H) ||
|
|
(format == NF_S) || (format == NF_D) ||
|
|
(format == NF_UNDEF));
|
|
static const char* formats[] = {
|
|
"undefined",
|
|
"undefined", "undefined", "undefined", "undefined",
|
|
"undefined", "undefined", "undefined", "undefined",
|
|
"'B", "'H", "'S", "'D"
|
|
};
|
|
return formats[format];
|
|
}
|
|
|
|
// Select bits from instrbits_ defined by the bits array, concatenate them,
|
|
// and return the value.
|
|
uint8_t PickBits(const uint8_t bits[]) {
|
|
uint8_t result = 0;
|
|
for (unsigned b = 0; b < kNEONFormatMaxBits; b++) {
|
|
if (bits[b] == 0) break;
|
|
result <<= 1;
|
|
result |= ((instrbits_ & (1 << bits[b])) == 0) ? 0 : 1;
|
|
}
|
|
return result;
|
|
}
|
|
|
|
Instr instrbits_;
|
|
const NEONFormatMap* formats_[3];
|
|
char form_buffer_[64];
|
|
char mne_buffer_[16];
|
|
};
|
|
} // namespace vixl
|
|
|
|
#endif // VIXL_A64_INSTRUCTIONS_A64_H_
|