Lara Lazier acf23ffb58 target/i386: Added DR6 and DR7 consistency checks ...

DR6[63:32] and DR7[63:32] are reserved and need to be zero.
(AMD64 Architecture Programmer's Manual, V2, 15.5)

Signed-off-by: Lara Lazier <laramglazier@gmail.com>
Message-Id: <20210705081802.18960-3-laramglazier@gmail.com>
[Ignore for 32-bit builds. - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

2021-07-09 18:21:33 +02:00

..

sysemu

target/i386: Added DR6 and DR7 consistency checks

2021-07-09 18:21:33 +02:00

user

target/i386: Remove user-only i/o stubs

2021-05-19 12:17:23 -05:00

bpt_helper.c

target/i386: Mark some helpers as noreturn

2021-05-19 12:17:11 -05:00

cc_helper_template.h

…

cc_helper.c

…

excp_helper.c

target/i386: Mark some helpers as noreturn

2021-05-19 12:17:11 -05:00

fpu_helper.c

target/i386: Move X86XSaveArea into TCG

2021-07-06 08:33:51 +02:00

helper-tcg.h

target/i386: Move invlpg, hlt, monitor, mwait to sysemu

2021-05-19 12:17:11 -05:00

int_helper.c

…

mem_helper.c

exec: Use cpu_untagged_addr in g2h; split out g2h_untagged

2021-02-16 11:04:53 +00:00

meson.build

i386: split svm_helper into sysemu and stub-only user

2021-05-10 15:41:51 -04:00

misc_helper.c

target/i386: Move invlpg, hlt, monitor, mwait to sysemu

2021-05-19 12:17:11 -05:00

mpx_helper.c

…

seg_helper.c

target/i386: tcg: fix switching from 16-bit to 32-bit tasks or vice versa

2021-06-04 13:47:08 +02:00

seg_helper.h

i386: split seg_helper into user-only and sysemu parts

2021-05-10 15:41:52 -04:00

tcg-cpu.c

target/i386: Populate x86_ext_save_areas offsets using cpuid where possible

2021-07-06 08:33:48 +02:00

tcg-cpu.h

target/i386: Move X86XSaveArea into TCG

2021-07-06 08:33:51 +02:00

tcg-stub.c

…

translate.c

target/i386: Improve bswap translation

2021-06-29 10:04:57 -07:00