424 lines
11 KiB
C
424 lines
11 KiB
C
/*
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* ARM implementation of KVM hooks, 64 bit specific code
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*
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* Copyright Mian-M. Hamayun 2013, Virtual Open Systems
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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*/
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#include <stdio.h>
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <sys/mman.h>
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#include <linux/kvm.h>
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#include "config-host.h"
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#include "qemu-common.h"
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#include "qemu/timer.h"
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#include "sysemu/sysemu.h"
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#include "sysemu/kvm.h"
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#include "kvm_arm.h"
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#include "cpu.h"
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#include "internals.h"
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#include "hw/arm/arm.h"
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static inline void set_feature(uint64_t *features, int feature)
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{
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*features |= 1ULL << feature;
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}
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bool kvm_arm_get_host_cpu_features(ARMHostCPUClass *ahcc)
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{
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/* Identify the feature bits corresponding to the host CPU, and
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* fill out the ARMHostCPUClass fields accordingly. To do this
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* we have to create a scratch VM, create a single CPU inside it,
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* and then query that CPU for the relevant ID registers.
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* For AArch64 we currently don't care about ID registers at
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* all; we just want to know the CPU type.
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*/
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int fdarray[3];
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uint64_t features = 0;
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/* Old kernels may not know about the PREFERRED_TARGET ioctl: however
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* we know these will only support creating one kind of guest CPU,
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* which is its preferred CPU type. Fortunately these old kernels
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* support only a very limited number of CPUs.
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*/
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static const uint32_t cpus_to_try[] = {
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KVM_ARM_TARGET_AEM_V8,
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KVM_ARM_TARGET_FOUNDATION_V8,
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KVM_ARM_TARGET_CORTEX_A57,
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QEMU_KVM_ARM_TARGET_NONE
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};
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struct kvm_vcpu_init init;
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if (!kvm_arm_create_scratch_host_vcpu(cpus_to_try, fdarray, &init)) {
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return false;
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}
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ahcc->target = init.target;
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ahcc->dtb_compatible = "arm,arm-v8";
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kvm_arm_destroy_scratch_host_vcpu(fdarray);
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/* We can assume any KVM supporting CPU is at least a v8
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* with VFPv4+Neon; this in turn implies most of the other
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* feature bits.
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*/
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set_feature(&features, ARM_FEATURE_V8);
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set_feature(&features, ARM_FEATURE_VFP4);
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set_feature(&features, ARM_FEATURE_NEON);
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set_feature(&features, ARM_FEATURE_AARCH64);
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ahcc->features = features;
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return true;
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}
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int kvm_arch_init_vcpu(CPUState *cs)
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{
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int ret;
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ARMCPU *cpu = ARM_CPU(cs);
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if (cpu->kvm_target == QEMU_KVM_ARM_TARGET_NONE ||
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!object_dynamic_cast(OBJECT(cpu), TYPE_AARCH64_CPU)) {
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fprintf(stderr, "KVM is not supported for this guest CPU type\n");
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return -EINVAL;
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}
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/* Determine init features for this CPU */
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memset(cpu->kvm_init_features, 0, sizeof(cpu->kvm_init_features));
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if (cpu->start_powered_off) {
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cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_POWER_OFF;
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}
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if (kvm_check_extension(cs->kvm_state, KVM_CAP_ARM_PSCI_0_2)) {
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cpu->psci_version = 2;
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cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_PSCI_0_2;
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}
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if (!arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
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cpu->kvm_init_features[0] |= 1 << KVM_ARM_VCPU_EL1_32BIT;
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}
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/* Do KVM_ARM_VCPU_INIT ioctl */
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ret = kvm_arm_vcpu_init(cs);
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if (ret) {
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return ret;
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}
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return kvm_arm_init_cpreg_list(cpu);
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}
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bool kvm_arm_reg_syncs_via_cpreg_list(uint64_t regidx)
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{
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/* Return true if the regidx is a register we should synchronize
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* via the cpreg_tuples array (ie is not a core reg we sync by
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* hand in kvm_arch_get/put_registers())
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*/
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switch (regidx & KVM_REG_ARM_COPROC_MASK) {
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case KVM_REG_ARM_CORE:
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return false;
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default:
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return true;
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}
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}
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#define AARCH64_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U64 | \
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
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#define AARCH64_SIMD_CORE_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U128 | \
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
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#define AARCH64_SIMD_CTRL_REG(x) (KVM_REG_ARM64 | KVM_REG_SIZE_U32 | \
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KVM_REG_ARM_CORE | KVM_REG_ARM_CORE_REG(x))
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int kvm_arch_put_registers(CPUState *cs, int level)
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{
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struct kvm_one_reg reg;
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uint32_t fpr;
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uint64_t val;
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int i;
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int ret;
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unsigned int el;
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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/* If we are in AArch32 mode then we need to copy the AArch32 regs to the
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* AArch64 registers before pushing them out to 64-bit KVM.
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*/
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if (!is_a64(env)) {
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aarch64_sync_32_to_64(env);
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}
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for (i = 0; i < 31; i++) {
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reg.id = AARCH64_CORE_REG(regs.regs[i]);
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reg.addr = (uintptr_t) &env->xregs[i];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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}
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/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
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* QEMU side we keep the current SP in xregs[31] as well.
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*/
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aarch64_save_sp(env, 1);
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reg.id = AARCH64_CORE_REG(regs.sp);
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reg.addr = (uintptr_t) &env->sp_el[0];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(sp_el1);
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reg.addr = (uintptr_t) &env->sp_el[1];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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/* Note that KVM thinks pstate is 64 bit but we use a uint32_t */
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if (is_a64(env)) {
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val = pstate_read(env);
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} else {
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val = cpsr_read(env);
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}
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reg.id = AARCH64_CORE_REG(regs.pstate);
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reg.addr = (uintptr_t) &val;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(regs.pc);
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reg.addr = (uintptr_t) &env->pc;
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(elr_el1);
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reg.addr = (uintptr_t) &env->elr_el[1];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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/* Saved Program State Registers
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*
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* Before we restore from the banked_spsr[] array we need to
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* ensure that any modifications to env->spsr are correctly
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* reflected in the banks.
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*/
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el = arm_current_el(env);
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if (el > 0 && !is_a64(env)) {
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i = bank_number(env->uncached_cpsr & CPSR_M);
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env->banked_spsr[i] = env->spsr;
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}
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/* KVM 0-4 map to QEMU banks 1-5 */
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for (i = 0; i < KVM_NR_SPSR; i++) {
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reg.id = AARCH64_CORE_REG(spsr[i]);
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reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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}
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/* Advanced SIMD and FP registers
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* We map Qn = regs[2n+1]:regs[2n]
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*/
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for (i = 0; i < 32; i++) {
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int rd = i << 1;
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uint64_t fp_val[2];
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#ifdef HOST_WORDS_BIGENDIAN
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fp_val[0] = env->vfp.regs[rd + 1];
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fp_val[1] = env->vfp.regs[rd];
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#else
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fp_val[1] = env->vfp.regs[rd + 1];
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fp_val[0] = env->vfp.regs[rd];
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#endif
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reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
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reg.addr = (uintptr_t)(&fp_val);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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}
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reg.addr = (uintptr_t)(&fpr);
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fpr = vfp_get_fpsr(env);
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reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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fpr = vfp_get_fpcr(env);
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reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
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ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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if (!write_list_to_kvmstate(cpu)) {
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return EINVAL;
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}
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kvm_arm_sync_mpstate_to_kvm(cpu);
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return ret;
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}
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int kvm_arch_get_registers(CPUState *cs)
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{
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struct kvm_one_reg reg;
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uint64_t val;
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uint32_t fpr;
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unsigned int el;
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int i;
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int ret;
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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for (i = 0; i < 31; i++) {
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reg.id = AARCH64_CORE_REG(regs.regs[i]);
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reg.addr = (uintptr_t) &env->xregs[i];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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}
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reg.id = AARCH64_CORE_REG(regs.sp);
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reg.addr = (uintptr_t) &env->sp_el[0];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(sp_el1);
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reg.addr = (uintptr_t) &env->sp_el[1];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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reg.id = AARCH64_CORE_REG(regs.pstate);
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reg.addr = (uintptr_t) &val;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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env->aarch64 = ((val & PSTATE_nRW) == 0);
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if (is_a64(env)) {
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pstate_write(env, val);
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} else {
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env->uncached_cpsr = val & CPSR_M;
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cpsr_write(env, val, 0xffffffff);
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}
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/* KVM puts SP_EL0 in regs.sp and SP_EL1 in regs.sp_el1. On the
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* QEMU side we keep the current SP in xregs[31] as well.
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*/
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aarch64_restore_sp(env, 1);
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reg.id = AARCH64_CORE_REG(regs.pc);
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reg.addr = (uintptr_t) &env->pc;
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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/* If we are in AArch32 mode then we need to sync the AArch32 regs with the
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* incoming AArch64 regs received from 64-bit KVM.
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* We must perform this after all of the registers have been acquired from
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* the kernel.
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*/
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if (!is_a64(env)) {
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aarch64_sync_64_to_32(env);
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}
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reg.id = AARCH64_CORE_REG(elr_el1);
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reg.addr = (uintptr_t) &env->elr_el[1];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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/* Fetch the SPSR registers
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*
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* KVM SPSRs 0-4 map to QEMU banks 1-5
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*/
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for (i = 0; i < KVM_NR_SPSR; i++) {
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reg.id = AARCH64_CORE_REG(spsr[i]);
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reg.addr = (uintptr_t) &env->banked_spsr[i + 1];
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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}
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el = arm_current_el(env);
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if (el > 0 && !is_a64(env)) {
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i = bank_number(env->uncached_cpsr & CPSR_M);
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env->spsr = env->banked_spsr[i];
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}
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/* Advanced SIMD and FP registers
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* We map Qn = regs[2n+1]:regs[2n]
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*/
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for (i = 0; i < 32; i++) {
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uint64_t fp_val[2];
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reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]);
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reg.addr = (uintptr_t)(&fp_val);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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} else {
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int rd = i << 1;
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#ifdef HOST_WORDS_BIGENDIAN
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env->vfp.regs[rd + 1] = fp_val[0];
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env->vfp.regs[rd] = fp_val[1];
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#else
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env->vfp.regs[rd + 1] = fp_val[1];
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env->vfp.regs[rd] = fp_val[0];
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#endif
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}
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}
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reg.addr = (uintptr_t)(&fpr);
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reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpsr);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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vfp_set_fpsr(env, fpr);
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reg.id = AARCH64_SIMD_CTRL_REG(fp_regs.fpcr);
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ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®);
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if (ret) {
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return ret;
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}
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vfp_set_fpcr(env, fpr);
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if (!write_kvmstate_to_list(cpu)) {
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return EINVAL;
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}
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/* Note that it's OK to have registers which aren't in CPUState,
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* so we can ignore a failure return here.
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*/
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write_list_to_cpustate(cpu);
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kvm_arm_sync_mpstate_to_qemu(cpu);
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/* TODO: other registers */
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return ret;
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}
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