ad5a5cf97d
According to the M68040 Users Manual, section 8.4.3, Six word stack frame (format 2), CHK, CHK2 (and others) are supposed to record the next insn in PC and the address of the trapping instruction in ADDRESS. Create a raise_exception_format2 function to centralize recording of the trapping pc in mmu.ar, plus advancing to the next insn. Update m68k_interrupt_all to pass mmu.ar to do_stack_frame. Update cpu_loop to pass mmu.ar to siginfo.si_addr, as the kernel does in trap_c(). Reviewed-by: Laurent Vivier <laurent@vivier.eu> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-Id: <20220602013401.303699-7-richard.henderson@linaro.org> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
126 lines
3.9 KiB
C
126 lines
3.9 KiB
C
/*
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* qemu user cpu loop
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu.h"
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#include "user-internals.h"
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#include "cpu_loop-common.h"
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#include "signal-common.h"
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void cpu_loop(CPUM68KState *env)
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{
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CPUState *cs = env_cpu(env);
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int trapnr;
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unsigned int n;
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for(;;) {
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cpu_exec_start(cs);
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trapnr = cpu_exec(cs);
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cpu_exec_end(cs);
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process_queued_cpu_work(cs);
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switch(trapnr) {
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case EXCP_HALT_INSN:
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/* Semihosing syscall. */
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env->pc += 4;
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do_m68k_semihosting(env, env->dregs[0]);
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break;
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case EXCP_ILLEGAL:
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case EXCP_LINEA:
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case EXCP_LINEF:
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPN, env->pc);
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break;
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case EXCP_CHK:
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force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTOVF, env->mmu.ar);
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break;
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case EXCP_DIV0:
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force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc);
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break;
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case EXCP_TRAP0:
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{
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abi_long ret;
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n = env->dregs[0];
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ret = do_syscall(env,
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n,
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env->dregs[1],
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env->dregs[2],
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env->dregs[3],
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env->dregs[4],
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env->dregs[5],
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env->aregs[0],
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0, 0);
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if (ret == -QEMU_ERESTARTSYS) {
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env->pc -= 2;
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} else if (ret != -QEMU_ESIGRETURN) {
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env->dregs[0] = ret;
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}
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}
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break;
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case EXCP_INTERRUPT:
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/* just indicate that signals should be handled asap */
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break;
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case EXCP_TRAP0 + 1 ... EXCP_TRAP0 + 14:
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force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc);
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break;
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case EXCP_DEBUG:
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case EXCP_TRAP15:
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force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc);
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break;
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case EXCP_ATOMIC:
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cpu_exec_step_atomic(cs);
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break;
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default:
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EXCP_DUMP(env, "qemu: unhandled CPU exception 0x%x - aborting\n", trapnr);
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abort();
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}
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process_pending_signals(env);
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}
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}
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void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs)
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{
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CPUState *cpu = env_cpu(env);
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TaskState *ts = cpu->opaque;
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struct image_info *info = ts->info;
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env->pc = regs->pc;
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env->dregs[0] = regs->d0;
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env->dregs[1] = regs->d1;
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env->dregs[2] = regs->d2;
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env->dregs[3] = regs->d3;
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env->dregs[4] = regs->d4;
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env->dregs[5] = regs->d5;
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env->dregs[6] = regs->d6;
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env->dregs[7] = regs->d7;
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env->aregs[0] = regs->a0;
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env->aregs[1] = regs->a1;
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env->aregs[2] = regs->a2;
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env->aregs[3] = regs->a3;
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env->aregs[4] = regs->a4;
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env->aregs[5] = regs->a5;
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env->aregs[6] = regs->a6;
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env->aregs[7] = regs->usp;
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env->sr = regs->sr;
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ts->stack_base = info->start_stack;
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ts->heap_base = info->brk;
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/* This will be filled in on the first SYS_HEAPINFO call. */
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ts->heap_limit = 0;
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}
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