Leon Alrae 5204ea79ea target-mips: add MTHC0 and MFHC0 instructions ... Implement MTHC0 and MFHC0 instructions. In MIPS32 they are used to access upper word of extended to 64-bits CP0 registers. In MIPS64, when CP0 destination register specified is the EntryLo0 or EntryLo1, bits 1:0 of the GPR appear at bits 31:30 of EntryLo0 or EntryLo1. This is to compensate for RI and XI, which were shifted to bits 63:62 by MTC0 to EntryLo0 or EntryLo1. Therefore creating separate functions for EntryLo0 and EntryLo1. Signed-off-by: Leon Alrae <leon.alrae@imgtec.com> Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>		2015-06-12 09:05:31 +01:00
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libvixl	disas/libvixl: Update to upstream VIXL 1.7	2015-02-05 13:37:25 +00:00
alpha.c
arm-a64.cc	disas/arm-a64.cc: Tell libvixl correct code addresses	2015-02-05 13:37:25 +00:00
arm.c	disas/arm: Fix warnings caused by missing 'static' attribute	2015-03-10 08:15:34 +03:00
cris.c	cris: remove unused cris_cond15 declarations	2015-03-19 11:11:55 +03:00
hppa.c
i386.c
ia64.c
lm32.c
m68k.c
Makefile.objs
microblaze.c	disas/microblaze: Fix warnings caused by missing 'static' attribute	2015-03-10 08:15:34 +03:00
mips.c	target-mips: add MTHC0 and MFHC0 instructions	2015-06-12 09:05:31 +01:00
moxie.c
ppc.c
s390.c	disas/s390.c: Remove unused variables	2015-02-03 12:27:05 -08:00
sh4.c	disas/sh4: Fix warning caused by missing 'static' attribute	2015-02-10 10:26:05 +03:00
sparc.c	disas/sparc: Remove unused data sparc_opcode_archs[]	2015-01-21 16:18:01 +00:00
tci.c