qemu-e2k/tests/tcg/xtensa
Max Filippov adbb3df08e tests/tcg/xtensa: update test_lsc for DFPU
DFPU doesn't have pre-increment FP load/store opcodes, it has
post-increment opcodes instead. Test increment opcodes present in the
current config.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2020-08-21 12:48:16 -07:00
..
crt.S
fpu.h
linker.ld.S
macros.inc
Makefile.softmmu-target
test_b.S
test_bi.S
test_boolean.S
test_break.S
test_bz.S
test_cache.S
test_clamps.S
test_exclusive.S
test_extui.S
test_flix.S
test_fp0_arith.S tests/tcg/xtensa: expand madd tests 2020-08-21 12:48:15 -07:00
test_fp0_conv.S tests/tcg/xtensa: update test_fp0_conv for DFPU 2020-08-21 12:48:16 -07:00
test_fp1.S tests/tcg/xtensa: update test_fp1 for DFPU 2020-08-21 12:48:16 -07:00
test_fp_cpenable.S
test_interrupt.S
test_loop.S
test_lsc.S tests/tcg/xtensa: update test_lsc for DFPU 2020-08-21 12:48:16 -07:00
test_mac16.S
test_max.S
test_min.S
test_mmu.S
test_mul16.S
test_mul32.S
test_nsa.S
test_phys_mem.S
test_quo.S
test_rem.S
test_rst0.S
test_s32c1i.S
test_sar.S
test_sext.S
test_shift.S
test_sr.S
test_timer.S
test_windowed.S
vectors.S