Peter Maydell aec4dd09f1 target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked) ... The MSR (banked) and MRS (banked) instructions allow accesses to ELR_Hyp from either Monitor or Hyp mode. Our translate time check was overly strict and only permitted access from Monitor mode. The runtime check we do in msr_mrs_banked_exc_checks() had the correct code in it, but never got there because of the earlier "currmode == tgtmode" check. Special case ELR_Hyp. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Reviewed-by: Luc Michel <luc.michel@greensocs.com> Message-id: 20180814124254.5229-9-peter.maydell@linaro.org		2018-08-20 11:24:32 +01:00
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alpha
arm	target/arm: Permit accesses to ELR_Hyp from Hyp mode via MSR/MRS (banked)	2018-08-20 11:24:32 +01:00
cris
hppa
i386	i386: Disable TOPOEXT by default on "-cpu host"	2018-08-16 13:43:01 -03:00
lm32
m68k	target/m68k: Merge disas_m68k_insn into m68k_tr_translate_insn	2018-06-11 12:43:42 +02:00
microblaze	target-microblaze: Rework NOP/zero instruction handling	2018-06-15 09:05:00 +02:00
mips	target/mips: Check ELPA flag only in some cases of MFHC0 and MTHC0	2018-08-16 19:18:45 +02:00
moxie
nios2
openrisc	target/openrisc: Fix writes to interrupt mask register	2018-07-03 22:40:33 +09:00
ppc	target/ppc: fix build on ppc64 host	2018-07-07 12:12:27 +10:00
riscv	RISC-V: Add trailing '\n' to qemu_log() calls	2018-06-08 13:15:33 +01:00
s390x	s390x/cpumodel: fix segmentation fault when baselining models	2018-07-18 14:20:02 +02:00
sh4	target/sh4: Fix translator.c assertion failure for gUSA	2018-07-09 10:34:04 -07:00
sparc	SPARC64: add icount support	2018-06-17 11:13:06 +01:00
tilegx
tricore
unicore32
xtensa	target/xtensa/cpu: Set owner of memory region in xtensa_cpu_initfn	2018-08-06 19:07:21 +01:00