Xuzhou Cheng d6bafaf45c hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips ... Now that the Xilinx CSU DMA model is implemented, the existing DMA related dead codes in the ZynqMP QSPI are useless and should be removed. The maximum register number is also updated to only include the QSPI registers. Signed-off-by: Xuzhou Cheng <xuzhou.cheng@windriver.com> Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Message-id: 20210303135254.3970-6-bmeng.cn@gmail.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2021-03-10 13:54:51 +00:00
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aspeed_smc.c
imx_spi.c	hw/ssi: imx_spi: Correct tx and rx fifo endianness	2021-02-02 17:00:55 +00:00
Kconfig	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
meson.build	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
mss-spi.c
npcm7xx_fiu.c	hw/*: Use type casting for SysBusDevice in NPCM7XX	2021-01-12 21:19:02 +00:00
omap_spi.c
pl022.c	hw/ssi: Rename SSI 'slave' as 'peripheral'	2020-12-10 12:15:03 -05:00
sifive_spi.c	hw/ssi: Add SiFive SPI controller support	2021-03-04 09:43:29 -05:00
ssi.c	hw/ssi: Rename SSI 'slave' as 'peripheral'	2020-12-10 12:15:03 -05:00
stm32f2xx_spi.c
trace-events
trace.h
xilinx_spi.c
xilinx_spips.c	hw/ssi: xilinx_spips: Remove DMA related dead codes from zynqmp_spips	2021-03-10 13:54:51 +00:00