LIU Zhiwei 6bf91617f4 target/riscv: configure and turn on vector extension from command line ...

Vector extension is default off. The only way to use vector extension is
1. use cpu rv32 or rv64
2. turn on it by command line
   "-cpu rv64,x-v=true,vlen=128,elen=64,vext_spec=v0.7.1".

vlen is the vector register length, default value is 128 bit.
elen is the max operator size in bits, default value is 64 bit.
vext_spec is the vector specification version, default value is v0.7.1.
These properties can be specified with other values.

Signed-off-by: LIU Zhiwei <zhiwei_liu@c-sky.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20200701152549.1218-62-zhiwei_liu@c-sky.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>

2020-07-02 09:19:34 -07:00

..

insn_trans

target/riscv: vector compress instruction

2020-07-02 09:19:34 -07:00

cpu_bits.h

target/riscv: support vector extension csr

2020-07-02 09:19:32 -07:00

cpu_helper.c

target/riscv: Report errors validating 2nd-stage PTEs

2020-06-19 08:24:07 -07:00

cpu_user.h

Supply missing header guards

2019-06-12 13:20:21 +02:00

cpu-param.h

tcg: Split out target/arch/cpu-param.h

2019-06-10 07:03:34 -07:00

cpu.c

target/riscv: configure and turn on vector extension from command line

2020-07-02 09:19:34 -07:00

cpu.h

target/riscv: configure and turn on vector extension from command line

2020-07-02 09:19:34 -07:00

csr.c

target/riscv: support vector extension csr

2020-07-02 09:19:32 -07:00

fpu_helper.c

target/riscv: vector floating-point classify instructions

2020-07-02 09:19:33 -07:00

gdbstub.c

gdbstub: extend GByteArray to read register helpers

2020-03-17 17:38:38 +00:00

helper.h

target/riscv: vector compress instruction

2020-07-02 09:19:34 -07:00

insn16-32.decode

target/riscv: Split RVC32 and RVC64 insns into separate files

2019-05-24 12:09:22 -07:00

insn16-64.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn16.decode

target/riscv: Add checks for several RVC reserved operands

2019-05-24 12:09:25 -07:00

insn32-64.decode

target/riscv: add vector amo operations

2020-07-02 09:19:33 -07:00

insn32.decode

target/riscv: vector compress instruction

2020-07-02 09:19:34 -07:00

instmap.h

target/riscv: progressively load the instruction during decode

2020-02-25 20:20:23 +00:00

internals.h

target/riscv: integer scalar move instruction

2020-07-02 09:19:33 -07:00

Makefile.objs

target/riscv: add vector configure instruction

2020-07-02 09:19:32 -07:00

monitor.c

target/riscv: Drop support for ISA spec version 1.09.1

2020-06-03 09:11:51 -07:00

op_helper.c

target/riscv: Implement checks for hfence

2020-06-19 08:24:07 -07:00

pmp.c

target/riscv: Use a smaller guess size for no-MMU PMP

2020-06-19 08:24:07 -07:00

pmp.h

RISC-V: Check for the effective memory privilege mode during PMP checks

2019-06-23 23:44:41 -07:00

trace-events

target/riscv/pmp: Convert qemu_log_mask(LOG_TRACE) to trace events

2019-09-17 08:42:42 -07:00

translate.c

target/riscv: add vector stride load and store instructions

2020-07-02 09:19:32 -07:00

vector_helper.c

target/riscv: vector compress instruction

2020-07-02 09:19:34 -07:00