Richard Henderson afc8b7d326 target/arm: Split helper_crypto_sha1_3reg ... Rather than passing an opcode to a helper, fully decode the operation at translate time. Use clear_tail_16 to zap the balance of the SVE register with the AdvSIMD write. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200514212831.31248-6-richard.henderson@linaro.org Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2020-06-05 17:23:09 +01:00
..
alpha
arm	target/arm: Split helper_crypto_sha1_3reg	2020-06-05 17:23:09 +01:00
cris
hppa
i386
lm32
m68k	target/m68k: implement opcode fetoxm1	2020-06-02 13:59:02 +02:00
microblaze
mips
moxie
nios2
openrisc
ppc	target/ppc: Use tcg_gen_gvec_rotlv	2020-06-02 08:42:37 -07:00
riscv	target/riscv: Add the lowRISC Ibex CPU	2020-06-03 09:11:51 -07:00
rx
s390x	target/s390x: Use tcg_gen_gvec_rotl{i,s,v}	2020-06-02 08:42:37 -07:00
sh4
sparc
tilegx
tricore	target/tricore: Implement gdbstub	2020-06-01 16:55:13 +02:00
unicore32
xtensa