430 lines
13 KiB
C
430 lines
13 KiB
C
/*
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* ARM Generic Interrupt Controller v3 (emulation)
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*
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* Copyright (c) 2015 Huawei.
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* Copyright (c) 2016 Linaro Limited
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* Written by Shlomo Pongratz, Peter Maydell
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*
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* This code is licensed under the GPL, version 2 or (at your option)
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* any later version.
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*/
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/* This file contains implementation code for an interrupt controller
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* which implements the GICv3 architecture. Specifically this is where
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* the device class itself and the functions for handling interrupts
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* coming in and going out live.
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*/
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#include "qemu/osdep.h"
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#include "qapi/error.h"
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#include "qemu/module.h"
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#include "hw/intc/arm_gicv3.h"
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#include "gicv3_internal.h"
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static bool irqbetter(GICv3CPUState *cs, int irq, uint8_t prio)
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{
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/* Return true if this IRQ at this priority should take
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* precedence over the current recorded highest priority
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* pending interrupt for this CPU. We also return true if
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* the current recorded highest priority pending interrupt
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* is the same as this one (a property which the calling code
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* relies on).
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*/
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if (prio < cs->hppi.prio) {
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return true;
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}
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/* If multiple pending interrupts have the same priority then it is an
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* IMPDEF choice which of them to signal to the CPU. We choose to
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* signal the one with the lowest interrupt number.
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*/
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if (prio == cs->hppi.prio && irq <= cs->hppi.irq) {
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return true;
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}
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return false;
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}
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static uint32_t gicd_int_pending(GICv3State *s, int irq)
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{
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/* Recalculate which distributor interrupts are actually pending
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* in the group of 32 interrupts starting at irq (which should be a multiple
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* of 32), and return a 32-bit integer which has a bit set for each
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* interrupt that is eligible to be signaled to the CPU interface.
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*
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* An interrupt is pending if:
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* + the PENDING latch is set OR it is level triggered and the input is 1
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* + its ENABLE bit is set
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* + the GICD enable bit for its group is set
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* + its ACTIVE bit is not set (otherwise it would be Active+Pending)
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* Conveniently we can bulk-calculate this with bitwise operations.
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*/
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uint32_t pend, grpmask;
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uint32_t pending = *gic_bmp_ptr32(s->pending, irq);
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uint32_t edge_trigger = *gic_bmp_ptr32(s->edge_trigger, irq);
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uint32_t level = *gic_bmp_ptr32(s->level, irq);
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uint32_t group = *gic_bmp_ptr32(s->group, irq);
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uint32_t grpmod = *gic_bmp_ptr32(s->grpmod, irq);
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uint32_t enable = *gic_bmp_ptr32(s->enabled, irq);
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uint32_t active = *gic_bmp_ptr32(s->active, irq);
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pend = pending | (~edge_trigger & level);
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pend &= enable;
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pend &= ~active;
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if (s->gicd_ctlr & GICD_CTLR_DS) {
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grpmod = 0;
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}
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grpmask = 0;
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if (s->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
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grpmask |= group;
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}
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if (s->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
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grpmask |= (~group & grpmod);
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}
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if (s->gicd_ctlr & GICD_CTLR_EN_GRP0) {
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grpmask |= (~group & ~grpmod);
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}
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pend &= grpmask;
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return pend;
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}
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static uint32_t gicr_int_pending(GICv3CPUState *cs)
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{
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/* Recalculate which redistributor interrupts are actually pending,
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* and return a 32-bit integer which has a bit set for each interrupt
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* that is eligible to be signaled to the CPU interface.
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*
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* An interrupt is pending if:
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* + the PENDING latch is set OR it is level triggered and the input is 1
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* + its ENABLE bit is set
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* + the GICD enable bit for its group is set
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* + its ACTIVE bit is not set (otherwise it would be Active+Pending)
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* Conveniently we can bulk-calculate this with bitwise operations.
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*/
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uint32_t pend, grpmask, grpmod;
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pend = cs->gicr_ipendr0 | (~cs->edge_trigger & cs->level);
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pend &= cs->gicr_ienabler0;
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pend &= ~cs->gicr_iactiver0;
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if (cs->gic->gicd_ctlr & GICD_CTLR_DS) {
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grpmod = 0;
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} else {
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grpmod = cs->gicr_igrpmodr0;
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}
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grpmask = 0;
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if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) {
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grpmask |= cs->gicr_igroupr0;
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}
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if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1S) {
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grpmask |= (~cs->gicr_igroupr0 & grpmod);
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}
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if (cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP0) {
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grpmask |= (~cs->gicr_igroupr0 & ~grpmod);
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}
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pend &= grpmask;
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return pend;
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}
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/* Update the interrupt status after state in a redistributor
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* or CPU interface has changed, but don't tell the CPU i/f.
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*/
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static void gicv3_redist_update_noirqset(GICv3CPUState *cs)
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{
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/* Find the highest priority pending interrupt among the
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* redistributor interrupts (SGIs and PPIs).
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*/
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bool seenbetter = false;
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uint8_t prio;
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int i;
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uint32_t pend;
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/* Find out which redistributor interrupts are eligible to be
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* signaled to the CPU interface.
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*/
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pend = gicr_int_pending(cs);
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if (pend) {
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for (i = 0; i < GIC_INTERNAL; i++) {
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if (!(pend & (1 << i))) {
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continue;
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}
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prio = cs->gicr_ipriorityr[i];
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if (irqbetter(cs, i, prio)) {
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cs->hppi.irq = i;
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cs->hppi.prio = prio;
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seenbetter = true;
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}
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}
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}
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if (seenbetter) {
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cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
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}
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if ((cs->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) && cs->gic->lpi_enable &&
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(cs->gic->gicd_ctlr & GICD_CTLR_EN_GRP1NS) &&
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(cs->hpplpi.prio != 0xff)) {
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if (irqbetter(cs, cs->hpplpi.irq, cs->hpplpi.prio)) {
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cs->hppi.irq = cs->hpplpi.irq;
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cs->hppi.prio = cs->hpplpi.prio;
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cs->hppi.grp = cs->hpplpi.grp;
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seenbetter = true;
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}
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}
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/* If the best interrupt we just found would preempt whatever
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* was the previous best interrupt before this update, then
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* we know it's definitely the best one now.
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* If we didn't find an interrupt that would preempt the previous
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* best, and the previous best is outside our range (or there was no
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* previous pending interrupt at all), then that is still valid, and
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* we leave it as the best.
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* Otherwise, we need to do a full update (because the previous best
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* interrupt has reduced in priority and any other interrupt could
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* now be the new best one).
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*/
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if (!seenbetter && cs->hppi.prio != 0xff &&
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(cs->hppi.irq < GIC_INTERNAL ||
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cs->hppi.irq >= GICV3_LPI_INTID_START)) {
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gicv3_full_update_noirqset(cs->gic);
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}
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}
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/* Update the GIC status after state in a redistributor or
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* CPU interface has changed, and inform the CPU i/f of
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* its new highest priority pending interrupt.
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*/
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void gicv3_redist_update(GICv3CPUState *cs)
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{
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gicv3_redist_update_noirqset(cs);
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gicv3_cpuif_update(cs);
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}
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/* Update the GIC status after state in the distributor has
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* changed affecting @len interrupts starting at @start,
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* but don't tell the CPU i/f.
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*/
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static void gicv3_update_noirqset(GICv3State *s, int start, int len)
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{
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int i;
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uint8_t prio;
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uint32_t pend = 0;
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assert(start >= GIC_INTERNAL);
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assert(len > 0);
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for (i = 0; i < s->num_cpu; i++) {
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s->cpu[i].seenbetter = false;
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}
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/* Find the highest priority pending interrupt in this range. */
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for (i = start; i < start + len; i++) {
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GICv3CPUState *cs;
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if (i == start || (i & 0x1f) == 0) {
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/* Calculate the next 32 bits worth of pending status */
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pend = gicd_int_pending(s, i & ~0x1f);
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}
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if (!(pend & (1 << (i & 0x1f)))) {
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continue;
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}
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cs = s->gicd_irouter_target[i];
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if (!cs) {
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/* Interrupts targeting no implemented CPU should remain pending
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* and not be forwarded to any CPU.
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*/
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continue;
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}
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prio = s->gicd_ipriority[i];
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if (irqbetter(cs, i, prio)) {
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cs->hppi.irq = i;
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cs->hppi.prio = prio;
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cs->seenbetter = true;
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}
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}
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/* If the best interrupt we just found would preempt whatever
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* was the previous best interrupt before this update, then
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* we know it's definitely the best one now.
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* If we didn't find an interrupt that would preempt the previous
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* best, and the previous best is outside our range (or there was
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* no previous pending interrupt at all), then that
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* is still valid, and we leave it as the best.
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* Otherwise, we need to do a full update (because the previous best
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* interrupt has reduced in priority and any other interrupt could
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* now be the new best one).
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*/
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for (i = 0; i < s->num_cpu; i++) {
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GICv3CPUState *cs = &s->cpu[i];
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if (cs->seenbetter) {
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cs->hppi.grp = gicv3_irq_group(cs->gic, cs, cs->hppi.irq);
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}
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if (!cs->seenbetter && cs->hppi.prio != 0xff &&
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cs->hppi.irq >= start && cs->hppi.irq < start + len) {
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gicv3_full_update_noirqset(s);
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break;
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}
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}
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}
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void gicv3_update(GICv3State *s, int start, int len)
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{
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int i;
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gicv3_update_noirqset(s, start, len);
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for (i = 0; i < s->num_cpu; i++) {
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gicv3_cpuif_update(&s->cpu[i]);
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}
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}
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void gicv3_full_update_noirqset(GICv3State *s)
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{
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/* Completely recalculate the GIC status from scratch, but
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* don't update any outbound IRQ lines.
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*/
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int i;
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for (i = 0; i < s->num_cpu; i++) {
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s->cpu[i].hppi.prio = 0xff;
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}
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/* Note that we can guarantee that these functions will not
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* recursively call back into gicv3_full_update(), because
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* at each point the "previous best" is always outside the
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* range we ask them to update.
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*/
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gicv3_update_noirqset(s, GIC_INTERNAL, s->num_irq - GIC_INTERNAL);
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for (i = 0; i < s->num_cpu; i++) {
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gicv3_redist_update_noirqset(&s->cpu[i]);
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}
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}
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void gicv3_full_update(GICv3State *s)
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{
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/* Completely recalculate the GIC status from scratch, including
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* updating outbound IRQ lines.
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*/
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int i;
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gicv3_full_update_noirqset(s);
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for (i = 0; i < s->num_cpu; i++) {
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gicv3_cpuif_update(&s->cpu[i]);
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}
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}
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/* Process a change in an external IRQ input. */
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static void gicv3_set_irq(void *opaque, int irq, int level)
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{
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/* Meaning of the 'irq' parameter:
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* [0..N-1] : external interrupts
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* [N..N+31] : PPI (internal) interrupts for CPU 0
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* [N+32..N+63] : PPI (internal interrupts for CPU 1
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* ...
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*/
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GICv3State *s = opaque;
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if (irq < (s->num_irq - GIC_INTERNAL)) {
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/* external interrupt (SPI) */
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gicv3_dist_set_irq(s, irq + GIC_INTERNAL, level);
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} else {
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/* per-cpu interrupt (PPI) */
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int cpu;
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irq -= (s->num_irq - GIC_INTERNAL);
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cpu = irq / GIC_INTERNAL;
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irq %= GIC_INTERNAL;
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assert(cpu < s->num_cpu);
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/* Raising SGIs via this function would be a bug in how the board
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* model wires up interrupts.
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*/
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assert(irq >= GIC_NR_SGIS);
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gicv3_redist_set_irq(&s->cpu[cpu], irq, level);
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}
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}
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static void arm_gicv3_post_load(GICv3State *s)
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{
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int i;
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/* Recalculate our cached idea of the current highest priority
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* pending interrupt, but don't set IRQ or FIQ lines.
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*/
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for (i = 0; i < s->num_cpu; i++) {
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gicv3_redist_update_lpi_only(&s->cpu[i]);
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}
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gicv3_full_update_noirqset(s);
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/* Repopulate the cache of GICv3CPUState pointers for target CPUs */
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gicv3_cache_all_target_cpustates(s);
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}
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static const MemoryRegionOps gic_ops[] = {
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{
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.read_with_attrs = gicv3_dist_read,
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.write_with_attrs = gicv3_dist_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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},
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{
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.read_with_attrs = gicv3_redist_read,
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.write_with_attrs = gicv3_redist_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid.min_access_size = 1,
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.valid.max_access_size = 8,
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.impl.min_access_size = 1,
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.impl.max_access_size = 8,
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}
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};
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static void arm_gic_realize(DeviceState *dev, Error **errp)
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{
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/* Device instance realize function for the GIC sysbus device */
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GICv3State *s = ARM_GICV3(dev);
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ARMGICv3Class *agc = ARM_GICV3_GET_CLASS(s);
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Error *local_err = NULL;
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agc->parent_realize(dev, &local_err);
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if (local_err) {
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error_propagate(errp, local_err);
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return;
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}
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gicv3_init_irqs_and_mmio(s, gicv3_set_irq, gic_ops);
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gicv3_init_cpuif(s);
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}
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static void arm_gicv3_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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ARMGICv3CommonClass *agcc = ARM_GICV3_COMMON_CLASS(klass);
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ARMGICv3Class *agc = ARM_GICV3_CLASS(klass);
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agcc->post_load = arm_gicv3_post_load;
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device_class_set_parent_realize(dc, arm_gic_realize, &agc->parent_realize);
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}
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static const TypeInfo arm_gicv3_info = {
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.name = TYPE_ARM_GICV3,
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.parent = TYPE_ARM_GICV3_COMMON,
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.instance_size = sizeof(GICv3State),
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.class_init = arm_gicv3_class_init,
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.class_size = sizeof(ARMGICv3Class),
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};
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static void arm_gicv3_register_types(void)
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{
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type_register_static(&arm_gicv3_info);
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}
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type_init(arm_gicv3_register_types)
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