qemu-e2k/target/arm
Peter Maydell 3448d47b31 translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD
For AArch32 LDREXD and STREXD, architecturally the 32-bit word at the
lowest address is always Rt and the one at addr+4 is Rt2, even if the
CPU is big-endian. Our implementation does these with a single
64-bit store, so if we're big-endian then we need to put the two
32-bit halves together in the opposite order to little-endian,
so that they end up in the right places. We were trying to do
this with the gen_aa32_frob64() function, but that is not correct
for the usermode emulator, because there there is a distinction
between "load a 64 bit value" (which does a BE 64-bit access
and doesn't need swapping) and "load two 32 bit values as one
64 bit access" (where we still need to do the swapping, like
system mode BE32).

Fixes: https://bugs.launchpad.net/qemu/+bug/1725267
Cc: qemu-stable@nongnu.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 1509622400-13351-1-git-send-email-peter.maydell@linaro.org
2017-11-07 13:03:51 +00:00
..
Makefile.objs Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
arch_dump.c hmp: fix "dump-quest-memory" segfault (arm) 2017-09-14 15:52:10 +01:00
arm-powerctl.c target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-powerctl.h target-arm/powerctl: defer cpu reset work to CPU context 2017-02-24 10:32:46 +00:00
arm-semi.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
arm_ldst.h Fix Thumb-1 BE32 execution and disassembly. 2017-02-07 18:29:59 +00:00
cpu-qom.h Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
cpu.c Capstone disassembler 2017-10-27 08:04:51 +01:00
cpu.h target/arm: Factor out "get mmuidx for specified security state" 2017-10-06 16:46:49 +01:00
cpu64.c target-arm: Enable EL2 feature bit on A53 and A57 2017-01-20 11:15:10 +00:00
crypto_helper.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
gdbstub.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
gdbstub64.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
helper-a64.c target/arm: check CF_PARALLEL instead of parallel_cpus 2017-10-24 13:53:41 -07:00
helper-a64.h target/arm: check CF_PARALLEL instead of parallel_cpus 2017-10-24 13:53:41 -07:00
helper.c arm: implement cache/shareability attribute bits for PAR registers 2017-11-07 13:03:51 +00:00
helper.h fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
internals.h fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
iwmmxt_helper.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
kvm-consts.h arm: add trailing ; after MISMATCH_CHECK 2017-02-01 03:37:18 +02:00
kvm-stub.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
kvm.c hw/arm/virt: allow pmu instantiation with userspace irqchip 2017-09-04 15:21:54 +01:00
kvm32.c target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm64.c target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
kvm_arm.h target/arm/kvm: pmu: improve error handling 2017-09-04 15:21:54 +01:00
machine.c nvic: Implement Security Attribution Unit registers 2017-10-06 16:46:49 +01:00
monitor.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
neon_helper.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
op_addsub.h Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
op_helper.c fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
psci.c fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
trace-events trace-events: fix code style: print 0x before hex numbers 2017-08-01 12:13:07 +01:00
translate-a64.c fix WFI/WFE length in syndrome register 2017-10-31 11:50:50 +00:00
translate.c translate.c: Fix usermode big-endian AArch32 LDREXD and STREXD 2017-11-07 13:03:51 +00:00
translate.h tcg: Initialize cpu_env generically 2017-10-24 13:53:42 -07:00