Richard Henderson e91a7227cb target/riscv: Split misa.mxl and misa.ext ... The hw representation of misa.mxl is at the high bits of the misa csr. Representing this in the same way inside QEMU results in overly complex code trying to check that field. Reviewed-by: LIU Zhiwei <zhiwei_liu@c-sky.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20211020031709.359469-4-richard.henderson@linaro.org Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2021-10-22 07:47:51 +10:00
..
cpu_loop.c	target/riscv: Split misa.mxl and misa.ext	2021-10-22 07:47:51 +10:00
signal.c	linux-user/riscv: Implement setup_sigtramp	2021-10-01 12:03:48 +02:00
sockbits.h
syscall32_nr.h	linux-user: update syscall_nr.h to Linux v5.13	2021-07-13 13:59:59 +02:00
syscall64_nr.h	linux-user: update syscall_nr.h to Linux v5.13	2021-07-13 13:59:59 +02:00
syscall_nr.h
target_cpu.h
target_elf.h
target_errno_defs.h	linux-user: Extract target errno to 'target_errno_defs.h'	2021-07-12 21:53:35 +02:00
target_fcntl.h
target_signal.h	linux-user/riscv: Implement setup_sigtramp	2021-10-01 12:03:48 +02:00
target_structs.h
target_syscall.h	linux-user: Add strace support for printing arguments of syscalls used to lock and unlock memory	2020-08-27 12:29:50 +02:00
termbits.h	linux-user: Add generic 'termbits.h' for some archs	2020-08-27 12:29:50 +02:00