qemu-e2k/target
David Hildenbrand b1ab5f6068 s390x/tcg: implement STOP and RESET interrupts for TCG
Implement them like KVM implements/handles them. Both can only be
triggered via SIGP instructions. RESET has (almost) the lowest priority if
the CPU is running, and the highest if the CPU is STOPPED. This is handled
in SIGP code already. On delivery, we only have to care about the
"CPU running" scenario.

STOP is defined to be delivered after all other interrupts have been
delivered. Therefore it has the actual lowest priority.

As both can wake up a CPU if sleeping, indicate them correctly to
external code (e.g. cpu_has_work()).

Signed-off-by: David Hildenbrand <david@redhat.com>
Message-Id: <20170928203708.9376-25-david@redhat.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Cornelia Huck <cohuck@redhat.com>
2017-10-20 13:32:10 +02:00
..
alpha tcg: remove addr argument from lookup_tb_ptr 2017-10-10 07:37:10 -07:00
arm target/arm: Implement SG instruction corner cases 2017-10-12 13:23:14 +01:00
cris qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
hppa tcg: remove addr argument from lookup_tb_ptr 2017-10-10 07:37:10 -07:00
i386 target/i386: trap on instructions longer than >15 bytes 2017-10-16 18:03:53 +02:00
lm32 qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
m68k qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
microblaze target: [tcg] Use a generic enum for DISAS_ values 2017-09-06 08:06:47 -07:00
mips linux-user: Tidy and enforce reserved_va initialization 2017-10-16 16:00:56 +03:00
moxie qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
nios2 * TCG 8-byte atomic accesses bugfix (Andrew) 2017-10-19 15:38:07 +01:00
openrisc qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
ppc * TCG 8-byte atomic accesses bugfix (Andrew) 2017-10-19 15:38:07 +01:00
s390x s390x/tcg: implement STOP and RESET interrupts for TCG 2017-10-20 13:32:10 +02:00
sh4 linux-user/sh4: Reduce TARGET_VIRT_ADDR_SPACE_BITS to 31 2017-10-16 16:00:56 +03:00
sparc qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
tilegx tilegx: replace cpu_tilegx_init() with cpu_generic_init() 2017-09-01 11:54:24 -03:00
tricore qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
unicore32 qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00
xtensa qom/cpu: move cpu_model null check to cpu_class_by_name() 2017-10-09 23:21:52 -03:00