qemu-e2k/docs/system
Peter Maydell 5959ef7d43 Fifth RISC-V PR for QEMU 7.0
* Fixup checks for ext_zb[abcs]
  * Add AIA support for virt machine
  * Increase maximum number of CPUs in virt machine
  * Fixup OpenTitan SPI address
  * Add support for zfinx, zdinx and zhinx{min} extensions
 -----BEGIN PGP SIGNATURE-----
 
 iQEzBAABCAAdFiEE9sSsRtSTSGjTuM6PIeENKd+XcFQFAmIgUZ8ACgkQIeENKd+X
 cFTzegf8DbUYFLpyfURm6bJoJfLQHjtjB4Hs6PnszJZZAEtC6Ia+551TDjh93vTf
 GTbpWm0BlugQqEeyg+Mioe2mb2EhK2w208RGXRSDjT9QFVOaIp83NDAjaQTPqs22
 XC35ygJYuo1Yf0WoJV77aB6IYPZB3ba5i+dkGb6lk60Ru5ULqoLvqp73tNe5KvNB
 uVAEy+ubzjmzWs5hGPw95HqTIbcMGnlHew4XU6xJaiJixSy71Z5nOCCn+2sxk+6A
 QW59Onglyfk01F9ac3GMLvi2e+FUdj0S0y07oVqchzxXWYpYwgTO4Xkt794c8mqU
 T02kuelfubr1qH1z/IolStju1JnaXw==
 =LzOY
 -----END PGP SIGNATURE-----

Merge remote-tracking branch 'remotes/alistair/tags/pull-riscv-to-apply-20220303' into staging

Fifth RISC-V PR for QEMU 7.0

 * Fixup checks for ext_zb[abcs]
 * Add AIA support for virt machine
 * Increase maximum number of CPUs in virt machine
 * Fixup OpenTitan SPI address
 * Add support for zfinx, zdinx and zhinx{min} extensions

# gpg: Signature made Thu 03 Mar 2022 05:26:55 GMT
# gpg:                using RSA key F6C4AC46D4934868D3B8CE8F21E10D29DF977054
# gpg: Good signature from "Alistair Francis <alistair@alistair23.me>" [full]
# Primary key fingerprint: F6C4 AC46 D493 4868 D3B8  CE8F 21E1 0D29 DF97 7054

* remotes/alistair/tags/pull-riscv-to-apply-20220303:
  target/riscv: expose zfinx, zdinx, zhinx{min} properties
  target/riscv: add support for zhinx/zhinxmin
  target/riscv: add support for zdinx
  target/riscv: add support for zfinx
  target/riscv: hardwire mstatus.FS to zero when enable zfinx
  target/riscv: add cfg properties for zfinx, zdinx and zhinx{min}
  hw: riscv: opentitan: fixup SPI addresses
  hw/riscv: virt: Increase maximum number of allowed CPUs
  docs/system: riscv: Document AIA options for virt machine
  hw/riscv: virt: Add optional AIA IMSIC support to virt machine
  hw/intc: Add RISC-V AIA IMSIC device emulation
  hw/riscv: virt: Add optional AIA APLIC support to virt machine
  target/riscv: fix inverted checks for ext_zb[abcs]

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
2022-03-03 19:59:38 +00:00
..
arm target/arm: Implement FEAT_LPA2 2022-03-02 19:27:37 +00:00
devices docs/can: convert to restructuredText 2022-01-20 11:47:52 +00:00
i386 docs: rstfy confidential guest documentation 2022-02-09 09:08:56 +01:00
ppc docs: rstfy confidential guest documentation 2022-02-09 09:08:56 +01:00
riscv docs/system: riscv: Document AIA options for virt machine 2022-03-03 13:14:50 +10:00
s390x
authz.rst docs: Drop deprecated 'props' from object-add 2021-11-22 15:02:38 +01:00
barrier.rst
bootindex.rst
confidential-guest-support.rst docs: rstfy confidential guest documentation 2022-02-09 09:08:56 +01:00
cpu-hotplug.rst
cpu-models-mips.rst.inc
cpu-models-x86-abi.csv
cpu-models-x86.rst.inc
device-emulation.rst docs/can: convert to restructuredText 2022-01-20 11:47:52 +00:00
device-url-syntax.rst.inc
gdb.rst
generic-loader.rst
guest-loader.rst
images.rst docs: Render binary names as monospaced text 2021-11-22 15:02:38 +01:00
index.rst docs: rstfy confidential guest documentation 2022-02-09 09:08:56 +01:00
invocation.rst
keys.rst
keys.rst.inc
linuxboot.rst
managed-startup.rst
monitor.rst
multi-process.rst
mux-chardev.rst
mux-chardev.rst.inc
pr-manager.rst
qemu-block-drivers.rst
qemu-block-drivers.rst.inc block: better document SSH host key fingerprint checking 2022-02-16 14:34:15 +00:00
qemu-cpu-models.rst
qemu-manpage.rst
quickstart.rst
secrets.rst
security.rst
target-arm.rst
target-avr.rst
target-i386-desc.rst.inc
target-i386.rst docs: rstfy confidential guest documentation 2022-02-09 09:08:56 +01:00
target-m68k.rst
target-mips.rst
target-ppc.rst
target-riscv.rst
target-rx.rst
target-s390x.rst
target-sparc64.rst
target-sparc.rst
target-xtensa.rst
targets.rst
tls.rst docs: Render binary names as monospaced text 2021-11-22 15:02:38 +01:00
virtio-net-failover.rst
vnc-security.rst