qemu-e2k/target/riscv
Daniel Henrique Barboza 560b8e1d70 target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr
KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() use an 'int ret' variable
that is used to do an early 'return' if ret > 0. Both are being called
in functions that are also declaring a 'ret' integer, initialized with
'0', and this integer is used as return of the function.

The result is that the compiler is less than pleased and is pointing
shadowing errors:

../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_get_regs_csr':
../target/riscv/kvm/kvm-cpu.c:90:13: error: declaration of 'ret' shadows a previous local [-Werror=shadow=compatible-local]
   90 |         int ret = kvm_get_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
      |             ^~~
../target/riscv/kvm/kvm-cpu.c:539:5: note: in expansion of macro 'KVM_RISCV_GET_CSR'
  539 |     KVM_RISCV_GET_CSR(cs, env, sstatus, env->mstatus);
      |     ^~~~~~~~~~~~~~~~~
../target/riscv/kvm/kvm-cpu.c:536:9: note: shadowed declaration is here
  536 |     int ret = 0;
      |         ^~~

../target/riscv/kvm/kvm-cpu.c: In function 'kvm_riscv_put_regs_csr':
../target/riscv/kvm/kvm-cpu.c:98:13: error: declaration of 'ret' shadows a previous local [-Werror=shadow=compatible-local]
   98 |         int ret = kvm_set_one_reg(cs, RISCV_CSR_REG(env, csr), &reg); \
      |             ^~~
../target/riscv/kvm/kvm-cpu.c:556:5: note: in expansion of macro 'KVM_RISCV_SET_CSR'
  556 |     KVM_RISCV_SET_CSR(cs, env, sstatus, env->mstatus);
      |     ^~~~~~~~~~~~~~~~~
../target/riscv/kvm/kvm-cpu.c:553:9: note: shadowed declaration is here
  553 |     int ret = 0;
      |         ^~~

The macros are doing early returns for non-zero returns and the local
'ret' variable for both functions is used just to do 'return 0', so
remove them from kvm_riscv_get_regs_csr() and kvm_riscv_put_regs_csr()
and do a straight 'return 0' in the end.

For good measure let's also rename the 'ret' variables in
KVM_RISCV_GET_CSR() and KVM_RISCV_SET_CSR() to '_ret' to make them more
resilient to these kind of errors.

Fixes: 937f0b4512 ("target/riscv: Implement kvm_arch_get_registers")
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Tested-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231123101338.1040134-1-dbarboza@ventanamicro.com>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
2023-12-04 16:21:00 +01:00
..
insn_trans target/riscv: Replace Zvbb checking by Zvkb 2023-11-07 11:06:02 +10:00
kvm target/riscv/kvm: fix shadowing in kvm_riscv_(get|put)_regs_csr 2023-12-04 16:21:00 +01:00
tcg target/riscv: don't verify ISA compatibility for zicntr and zihpm 2023-11-22 13:56:13 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h target/riscv: Add M-mode virtual interrupt and IRQ filtering support. 2023-11-07 11:02:17 +10:00
cpu_cfg.h target/riscv: Add "pmu-mask" property to replace "pmu-num" 2023-11-07 11:06:02 +10:00
cpu_helper.c target/riscv/cpu_helper.c: Fix mxr bit behavior 2023-11-22 14:03:37 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h target: Move ArchCPUClass definition to 'cpu.h' 2023-11-07 13:08:48 +01:00
cpu.c hw/cpu: Call object_class_is_abstract() once in cpu_class_by_name() 2023-11-07 13:08:48 +01:00
cpu.h target/riscv/cpu.h: spelling fix: separatly 2023-11-15 12:06:05 +03:00
crypto_helper.c
csr.c target/riscv: Don't assume PMU counters are continuous 2023-11-07 11:06:02 +10:00
debug.c target/riscv: Allocate itrigger timers only once 2023-09-11 11:45:55 +10:00
debug.h target/riscv: Allocate itrigger timers only once 2023-09-11 11:45:55 +10:00
fpu_helper.c
gdbstub.c target/riscv: rename ext_icsr to ext_zicsr 2023-11-07 11:02:17 +10:00
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h target/riscv: Use env_archcpu() in [check_]nanbox() 2023-11-07 12:13:27 +01:00
Kconfig
m128_helper.c
machine.c target/riscv: Add "pmu-mask" property to replace "pmu-num" 2023-11-07 11:06:02 +10:00
meson.build target/riscv: move KVM only files to kvm subdir 2023-10-12 12:20:24 +10:00
monitor.c
op_helper.c
pmp.c target/riscv: pmp: Ignore writes when RW=01 2023-11-07 11:06:02 +10:00
pmp.h target/riscv: pmp: Clear pmp/smepmp bits on reset 2023-11-07 11:06:02 +10:00
pmu.c target/riscv: Add "pmu-mask" property to replace "pmu-num" 2023-11-07 11:06:02 +10:00
pmu.h target/riscv: Use existing PMU counter mask in FDT generation 2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion 2023-11-07 11:06:02 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c accel/tcg: Replace CPUState.env_ptr with cpu_env() 2023-10-04 11:03:54 -07:00
vcrypto_helper.c
vector_helper.c target/riscv: Fix vfwmaccbf16.vf 2023-10-12 12:50:13 +10:00
vector_internals.c
vector_internals.h
xthead.decode
XVentanaCondOps.decode
zce_helper.c