Jonathan Cameron 882877fc35 hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE ... This Data Object Exchange Mailbox allows software to query the latency and bandwidth between ports on the switch. For now only provide information on routes between the upstream port and each downstream port (not p2p). Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> -- Changes since v8: Mostly to match the type 3 equivalent - Move enum out of function and give it a more descriptive namespace. Message-Id: <20221014151045.24781-6-Jonathan.Cameron@huawei.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>		2022-11-07 13:12:19 -05:00
..
cxl_downstream.c	pci-bridge/cxl_downstream: Add a CXL switch downstream port	2022-06-16 12:54:57 -04:00
cxl_root_port.c	hw/cxl/rp: Add a root port	2022-05-13 06:13:36 -04:00
cxl_upstream.c	hw/pci-bridge/cxl-upstream: Add a CDAT table access DOE	2022-11-07 13:12:19 -05:00
dec.c
dec.h
gen_pcie_root_port.c	hw/pcie-root-port: Fix hotplug for PCI devices requiring IO	2021-08-03 16:31:07 -04:00
i82801b11.c
ioh3420.c
Kconfig	hw/cxl/rp: Add a root port	2022-05-13 06:13:36 -04:00
meson.build	pci-bridge/cxl_downstream: Add a CXL switch downstream port	2022-06-16 12:54:57 -04:00
pci_bridge_dev.c
pci_expander_bridge_stubs.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
pci_expander_bridge.c	pci/pci_expander_bridge: For CXL HB delay the HB register memory region setup.	2022-06-09 19:32:49 -04:00
pcie_pci_bridge.c
pcie_root_port.c	hw/cxl/rp: Add a root port	2022-05-13 06:13:36 -04:00
simba.c
xio3130_downstream.c	pci: expose TYPE_XIO3130_DOWNSTREAM name	2022-03-06 05:08:23 -05:00
xio3130_upstream.c	pci-bridge/xio3130_upstream: Fix error handling	2022-03-06 05:08:23 -05:00