7bedee3243
Now that load/store are gone, we're always passing PAGE_READ | PAGE_WRITE for RMW atomic operations. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
280 lines
9.7 KiB
C
280 lines
9.7 KiB
C
/*
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* Atomic helper templates
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* Included from tcg-runtime.c and cputlb.c.
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*
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* Copyright (c) 2016 Red Hat, Inc
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/plugin.h"
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#if DATA_SIZE == 16
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# define SUFFIX o
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# define DATA_TYPE Int128
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# define BSWAP bswap128
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# define SHIFT 4
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#elif DATA_SIZE == 8
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# define SUFFIX q
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# define DATA_TYPE aligned_uint64_t
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# define SDATA_TYPE aligned_int64_t
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# define BSWAP bswap64
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# define SHIFT 3
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#elif DATA_SIZE == 4
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# define SUFFIX l
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# define DATA_TYPE uint32_t
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# define SDATA_TYPE int32_t
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# define BSWAP bswap32
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# define SHIFT 2
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#elif DATA_SIZE == 2
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# define SUFFIX w
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# define DATA_TYPE uint16_t
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# define SDATA_TYPE int16_t
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# define BSWAP bswap16
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# define SHIFT 1
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#elif DATA_SIZE == 1
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# define SUFFIX b
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# define DATA_TYPE uint8_t
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# define SDATA_TYPE int8_t
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# define BSWAP
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# define SHIFT 0
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#else
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# error unsupported data size
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#endif
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#if DATA_SIZE >= 4
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# define ABI_TYPE DATA_TYPE
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#else
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# define ABI_TYPE uint32_t
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#endif
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/* Define host-endian atomic operations. Note that END is used within
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the ATOMIC_NAME macro, and redefined below. */
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#if DATA_SIZE == 1
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# define END
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#elif HOST_BIG_ENDIAN
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# define END _be
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#else
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# define END _le
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#endif
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ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE cmpv, ABI_TYPE newv,
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
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DATA_TYPE ret;
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#if DATA_SIZE == 16
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ret = atomic16_cmpxchg(haddr, cmpv, newv);
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#else
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ret = qatomic_cmpxchg__nocheck(haddr, cmpv, newv);
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#endif
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ATOMIC_MMU_CLEANUP;
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atomic_trace_rmw_post(env, addr, oi);
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return ret;
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}
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#if DATA_SIZE < 16
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
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DATA_TYPE ret;
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ret = qatomic_xchg__nocheck(haddr, val);
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ATOMIC_MMU_CLEANUP;
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atomic_trace_rmw_post(env, addr, oi);
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return ret;
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}
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#define GEN_ATOMIC_HELPER(X) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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DATA_TYPE *haddr, ret; \
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haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
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ret = qatomic_##X(haddr, val); \
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ATOMIC_MMU_CLEANUP; \
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atomic_trace_rmw_post(env, addr, oi); \
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return ret; \
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}
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GEN_ATOMIC_HELPER(fetch_add)
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GEN_ATOMIC_HELPER(fetch_and)
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GEN_ATOMIC_HELPER(fetch_or)
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GEN_ATOMIC_HELPER(fetch_xor)
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GEN_ATOMIC_HELPER(add_fetch)
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GEN_ATOMIC_HELPER(and_fetch)
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GEN_ATOMIC_HELPER(or_fetch)
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GEN_ATOMIC_HELPER(xor_fetch)
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#undef GEN_ATOMIC_HELPER
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/*
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* These helpers are, as a whole, full barriers. Within the helper,
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* the leading barrier is explicit and the trailing barrier is within
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* cmpxchg primitive.
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*
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* Trace this load + RMW loop as a single RMW op. This way, regardless
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* of CF_PARALLEL's value, we'll trace just a read and a write.
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*/
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#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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XDATA_TYPE *haddr, cmp, old, new, val = xval; \
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haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
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smp_mb(); \
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cmp = qatomic_read__nocheck(haddr); \
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do { \
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old = cmp; new = FN(old, val); \
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cmp = qatomic_cmpxchg__nocheck(haddr, old, new); \
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} while (cmp != old); \
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ATOMIC_MMU_CLEANUP; \
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atomic_trace_rmw_post(env, addr, oi); \
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return RET; \
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}
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GEN_ATOMIC_HELPER_FN(fetch_smin, MIN, SDATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(fetch_umin, MIN, DATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(fetch_smax, MAX, SDATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(fetch_umax, MAX, DATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(smin_fetch, MIN, SDATA_TYPE, new)
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GEN_ATOMIC_HELPER_FN(umin_fetch, MIN, DATA_TYPE, new)
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GEN_ATOMIC_HELPER_FN(smax_fetch, MAX, SDATA_TYPE, new)
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GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new)
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#undef GEN_ATOMIC_HELPER_FN
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#endif /* DATA SIZE < 16 */
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#undef END
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#if DATA_SIZE > 1
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/* Define reverse-host-endian atomic operations. Note that END is used
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within the ATOMIC_NAME macro. */
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#if HOST_BIG_ENDIAN
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# define END _le
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#else
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# define END _be
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#endif
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ABI_TYPE ATOMIC_NAME(cmpxchg)(CPUArchState *env, target_ulong addr,
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ABI_TYPE cmpv, ABI_TYPE newv,
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
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DATA_TYPE ret;
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#if DATA_SIZE == 16
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ret = atomic16_cmpxchg(haddr, BSWAP(cmpv), BSWAP(newv));
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#else
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ret = qatomic_cmpxchg__nocheck(haddr, BSWAP(cmpv), BSWAP(newv));
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#endif
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ATOMIC_MMU_CLEANUP;
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atomic_trace_rmw_post(env, addr, oi);
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return BSWAP(ret);
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}
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#if DATA_SIZE < 16
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ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, ABI_TYPE val,
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MemOpIdx oi, uintptr_t retaddr)
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{
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DATA_TYPE *haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr);
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ABI_TYPE ret;
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ret = qatomic_xchg__nocheck(haddr, BSWAP(val));
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ATOMIC_MMU_CLEANUP;
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atomic_trace_rmw_post(env, addr, oi);
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return BSWAP(ret);
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}
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#define GEN_ATOMIC_HELPER(X) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE val, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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DATA_TYPE *haddr, ret; \
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haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
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ret = qatomic_##X(haddr, BSWAP(val)); \
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ATOMIC_MMU_CLEANUP; \
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atomic_trace_rmw_post(env, addr, oi); \
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return BSWAP(ret); \
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}
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GEN_ATOMIC_HELPER(fetch_and)
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GEN_ATOMIC_HELPER(fetch_or)
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GEN_ATOMIC_HELPER(fetch_xor)
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GEN_ATOMIC_HELPER(and_fetch)
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GEN_ATOMIC_HELPER(or_fetch)
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GEN_ATOMIC_HELPER(xor_fetch)
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#undef GEN_ATOMIC_HELPER
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/* These helpers are, as a whole, full barriers. Within the helper,
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* the leading barrier is explicit and the trailing barrier is within
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* cmpxchg primitive.
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*
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* Trace this load + RMW loop as a single RMW op. This way, regardless
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* of CF_PARALLEL's value, we'll trace just a read and a write.
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*/
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#define GEN_ATOMIC_HELPER_FN(X, FN, XDATA_TYPE, RET) \
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ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \
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ABI_TYPE xval, MemOpIdx oi, uintptr_t retaddr) \
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{ \
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XDATA_TYPE *haddr, ldo, ldn, old, new, val = xval; \
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haddr = atomic_mmu_lookup(env, addr, oi, DATA_SIZE, retaddr); \
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smp_mb(); \
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ldn = qatomic_read__nocheck(haddr); \
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do { \
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ldo = ldn; old = BSWAP(ldo); new = FN(old, val); \
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ldn = qatomic_cmpxchg__nocheck(haddr, ldo, BSWAP(new)); \
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} while (ldo != ldn); \
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ATOMIC_MMU_CLEANUP; \
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atomic_trace_rmw_post(env, addr, oi); \
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return RET; \
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}
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GEN_ATOMIC_HELPER_FN(fetch_smin, MIN, SDATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(fetch_umin, MIN, DATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(fetch_smax, MAX, SDATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(fetch_umax, MAX, DATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(smin_fetch, MIN, SDATA_TYPE, new)
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GEN_ATOMIC_HELPER_FN(umin_fetch, MIN, DATA_TYPE, new)
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GEN_ATOMIC_HELPER_FN(smax_fetch, MAX, SDATA_TYPE, new)
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GEN_ATOMIC_HELPER_FN(umax_fetch, MAX, DATA_TYPE, new)
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/* Note that for addition, we need to use a separate cmpxchg loop instead
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of bswaps for the reverse-host-endian helpers. */
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#define ADD(X, Y) (X + Y)
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GEN_ATOMIC_HELPER_FN(fetch_add, ADD, DATA_TYPE, old)
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GEN_ATOMIC_HELPER_FN(add_fetch, ADD, DATA_TYPE, new)
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#undef ADD
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#undef GEN_ATOMIC_HELPER_FN
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#endif /* DATA_SIZE < 16 */
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#undef END
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#endif /* DATA_SIZE > 1 */
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#undef BSWAP
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#undef ABI_TYPE
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#undef DATA_TYPE
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#undef SDATA_TYPE
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#undef SUFFIX
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#undef DATA_SIZE
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#undef SHIFT
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