3ff6fc9148
Implement the ARM debug exception handler for dealing with fired watchpoints. Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
712 lines
19 KiB
C
712 lines
19 KiB
C
/*
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* ARM helper routines
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*
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* Copyright (c) 2005-2007 CodeSourcery, LLC
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "cpu.h"
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#include "exec/helper-proto.h"
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#include "internals.h"
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#include "exec/cpu_ldst.h"
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#define SIGNBIT (uint32_t)0x80000000
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#define SIGNBIT64 ((uint64_t)1 << 63)
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static void raise_exception(CPUARMState *env, int tt)
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{
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ARMCPU *cpu = arm_env_get_cpu(env);
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CPUState *cs = CPU(cpu);
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cs->exception_index = tt;
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cpu_loop_exit(cs);
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}
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uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def,
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uint32_t rn, uint32_t maxindex)
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{
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uint32_t val;
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uint32_t tmp;
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int index;
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int shift;
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uint64_t *table;
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table = (uint64_t *)&env->vfp.regs[rn];
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val = 0;
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for (shift = 0; shift < 32; shift += 8) {
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index = (ireg >> shift) & 0xff;
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if (index < maxindex) {
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tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff;
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val |= tmp << shift;
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} else {
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val |= def & (0xff << shift);
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}
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}
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return val;
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}
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#if !defined(CONFIG_USER_ONLY)
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/* try to fill the TLB and return an exception if error. If retaddr is
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* NULL, it means that the function was called in C code (i.e. not
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* from generated code or from helper.c)
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*/
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void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
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uintptr_t retaddr)
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{
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int ret;
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ret = arm_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
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if (unlikely(ret)) {
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ARMCPU *cpu = ARM_CPU(cs);
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CPUARMState *env = &cpu->env;
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if (retaddr) {
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/* now we have a real cpu fault */
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cpu_restore_state(cs, retaddr);
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}
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raise_exception(env, cs->exception_index);
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}
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}
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#endif
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uint32_t HELPER(add_setq)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT))
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env->QF = 1;
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return res;
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}
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uint32_t HELPER(add_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
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env->QF = 1;
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res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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}
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return res;
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}
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uint32_t HELPER(sub_saturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a - b;
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if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
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env->QF = 1;
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res = ~(((int32_t)a >> 31) ^ SIGNBIT);
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}
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return res;
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}
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uint32_t HELPER(double_saturate)(CPUARMState *env, int32_t val)
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{
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uint32_t res;
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if (val >= 0x40000000) {
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res = ~SIGNBIT;
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env->QF = 1;
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} else if (val <= (int32_t)0xc0000000) {
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res = SIGNBIT;
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env->QF = 1;
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} else {
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res = val << 1;
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}
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return res;
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}
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uint32_t HELPER(add_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a + b;
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if (res < a) {
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env->QF = 1;
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res = ~0;
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}
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return res;
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}
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uint32_t HELPER(sub_usaturate)(CPUARMState *env, uint32_t a, uint32_t b)
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{
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uint32_t res = a - b;
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if (res > a) {
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env->QF = 1;
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res = 0;
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}
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return res;
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}
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/* Signed saturation. */
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static inline uint32_t do_ssat(CPUARMState *env, int32_t val, int shift)
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{
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int32_t top;
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uint32_t mask;
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top = val >> shift;
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mask = (1u << shift) - 1;
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if (top > 0) {
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env->QF = 1;
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return mask;
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} else if (top < -1) {
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env->QF = 1;
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return ~mask;
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}
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return val;
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}
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/* Unsigned saturation. */
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static inline uint32_t do_usat(CPUARMState *env, int32_t val, int shift)
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{
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uint32_t max;
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max = (1u << shift) - 1;
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if (val < 0) {
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env->QF = 1;
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return 0;
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} else if (val > max) {
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env->QF = 1;
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return max;
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}
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return val;
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}
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/* Signed saturate. */
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uint32_t HELPER(ssat)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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return do_ssat(env, x, shift);
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}
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/* Dual halfword signed saturate. */
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uint32_t HELPER(ssat16)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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uint32_t res;
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res = (uint16_t)do_ssat(env, (int16_t)x, shift);
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res |= do_ssat(env, ((int32_t)x) >> 16, shift) << 16;
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return res;
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}
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/* Unsigned saturate. */
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uint32_t HELPER(usat)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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return do_usat(env, x, shift);
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}
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/* Dual halfword unsigned saturate. */
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uint32_t HELPER(usat16)(CPUARMState *env, uint32_t x, uint32_t shift)
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{
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uint32_t res;
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res = (uint16_t)do_usat(env, (int16_t)x, shift);
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res |= do_usat(env, ((int32_t)x) >> 16, shift) << 16;
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return res;
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}
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void HELPER(wfi)(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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cs->exception_index = EXCP_HLT;
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cs->halted = 1;
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cpu_loop_exit(cs);
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}
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void HELPER(wfe)(CPUARMState *env)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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/* Don't actually halt the CPU, just yield back to top
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* level loop
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*/
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cs->exception_index = EXCP_YIELD;
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cpu_loop_exit(cs);
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}
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/* Raise an internal-to-QEMU exception. This is limited to only
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* those EXCP values which are special cases for QEMU to interrupt
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* execution and not to be used for exceptions which are passed to
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* the guest (those must all have syndrome information and thus should
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* use exception_with_syndrome).
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*/
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void HELPER(exception_internal)(CPUARMState *env, uint32_t excp)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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assert(excp_is_internal(excp));
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cs->exception_index = excp;
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cpu_loop_exit(cs);
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}
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/* Raise an exception with the specified syndrome register value */
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void HELPER(exception_with_syndrome)(CPUARMState *env, uint32_t excp,
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uint32_t syndrome)
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{
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CPUState *cs = CPU(arm_env_get_cpu(env));
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assert(!excp_is_internal(excp));
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cs->exception_index = excp;
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env->exception.syndrome = syndrome;
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cpu_loop_exit(cs);
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}
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uint32_t HELPER(cpsr_read)(CPUARMState *env)
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{
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return cpsr_read(env) & ~(CPSR_EXEC | CPSR_RESERVED);
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}
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void HELPER(cpsr_write)(CPUARMState *env, uint32_t val, uint32_t mask)
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{
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cpsr_write(env, val, mask);
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}
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/* Access to user mode registers from privileged modes. */
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uint32_t HELPER(get_user_reg)(CPUARMState *env, uint32_t regno)
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{
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uint32_t val;
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if (regno == 13) {
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val = env->banked_r13[0];
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} else if (regno == 14) {
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val = env->banked_r14[0];
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} else if (regno >= 8
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&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
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val = env->usr_regs[regno - 8];
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} else {
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val = env->regs[regno];
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}
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return val;
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}
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void HELPER(set_user_reg)(CPUARMState *env, uint32_t regno, uint32_t val)
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{
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if (regno == 13) {
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env->banked_r13[0] = val;
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} else if (regno == 14) {
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env->banked_r14[0] = val;
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} else if (regno >= 8
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&& (env->uncached_cpsr & 0x1f) == ARM_CPU_MODE_FIQ) {
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env->usr_regs[regno - 8] = val;
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} else {
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env->regs[regno] = val;
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}
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}
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void HELPER(access_check_cp_reg)(CPUARMState *env, void *rip, uint32_t syndrome)
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{
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const ARMCPRegInfo *ri = rip;
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switch (ri->accessfn(env, ri)) {
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case CP_ACCESS_OK:
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return;
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case CP_ACCESS_TRAP:
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env->exception.syndrome = syndrome;
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break;
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case CP_ACCESS_TRAP_UNCATEGORIZED:
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env->exception.syndrome = syn_uncategorized();
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break;
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default:
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g_assert_not_reached();
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}
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raise_exception(env, EXCP_UDEF);
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}
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void HELPER(set_cp_reg)(CPUARMState *env, void *rip, uint32_t value)
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{
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const ARMCPRegInfo *ri = rip;
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ri->writefn(env, ri, value);
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}
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uint32_t HELPER(get_cp_reg)(CPUARMState *env, void *rip)
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{
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const ARMCPRegInfo *ri = rip;
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return ri->readfn(env, ri);
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}
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void HELPER(set_cp_reg64)(CPUARMState *env, void *rip, uint64_t value)
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{
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const ARMCPRegInfo *ri = rip;
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ri->writefn(env, ri, value);
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}
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uint64_t HELPER(get_cp_reg64)(CPUARMState *env, void *rip)
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{
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const ARMCPRegInfo *ri = rip;
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return ri->readfn(env, ri);
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}
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void HELPER(msr_i_pstate)(CPUARMState *env, uint32_t op, uint32_t imm)
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{
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/* MSR_i to update PSTATE. This is OK from EL0 only if UMA is set.
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* Note that SPSel is never OK from EL0; we rely on handle_msr_i()
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* to catch that case at translate time.
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*/
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if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
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raise_exception(env, EXCP_UDEF);
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}
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switch (op) {
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case 0x05: /* SPSel */
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update_spsel(env, imm);
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break;
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case 0x1e: /* DAIFSet */
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env->daif |= (imm << 6) & PSTATE_DAIF;
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break;
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case 0x1f: /* DAIFClear */
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env->daif &= ~((imm << 6) & PSTATE_DAIF);
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break;
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default:
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g_assert_not_reached();
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}
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}
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void HELPER(clear_pstate_ss)(CPUARMState *env)
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{
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env->pstate &= ~PSTATE_SS;
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}
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void HELPER(exception_return)(CPUARMState *env)
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{
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int cur_el = arm_current_pl(env);
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unsigned int spsr_idx = aarch64_banked_spsr_index(cur_el);
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uint32_t spsr = env->banked_spsr[spsr_idx];
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int new_el, i;
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aarch64_save_sp(env, cur_el);
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env->exclusive_addr = -1;
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/* We must squash the PSTATE.SS bit to zero unless both of the
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* following hold:
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* 1. debug exceptions are currently disabled
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* 2. singlestep will be active in the EL we return to
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* We check 1 here and 2 after we've done the pstate/cpsr write() to
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* transition to the EL we're going to.
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*/
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if (arm_generate_debug_exceptions(env)) {
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spsr &= ~PSTATE_SS;
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}
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if (spsr & PSTATE_nRW) {
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/* TODO: We currently assume EL1/2/3 are running in AArch64. */
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env->aarch64 = 0;
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new_el = 0;
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env->uncached_cpsr = 0x10;
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cpsr_write(env, spsr, ~0);
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if (!arm_singlestep_active(env)) {
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env->uncached_cpsr &= ~PSTATE_SS;
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}
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for (i = 0; i < 15; i++) {
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env->regs[i] = env->xregs[i];
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}
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env->regs[15] = env->elr_el[1] & ~0x1;
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} else {
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new_el = extract32(spsr, 2, 2);
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if (new_el > cur_el
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|| (new_el == 2 && !arm_feature(env, ARM_FEATURE_EL2))) {
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/* Disallow return to an EL which is unimplemented or higher
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* than the current one.
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*/
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goto illegal_return;
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}
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if (extract32(spsr, 1, 1)) {
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/* Return with reserved M[1] bit set */
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goto illegal_return;
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}
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if (new_el == 0 && (spsr & PSTATE_SP)) {
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/* Return to EL0 with M[0] bit set */
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goto illegal_return;
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}
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env->aarch64 = 1;
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pstate_write(env, spsr);
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if (!arm_singlestep_active(env)) {
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env->pstate &= ~PSTATE_SS;
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}
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aarch64_restore_sp(env, new_el);
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env->pc = env->elr_el[cur_el];
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}
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return;
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illegal_return:
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/* Illegal return events of various kinds have architecturally
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* mandated behaviour:
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* restore NZCV and DAIF from SPSR_ELx
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* set PSTATE.IL
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* restore PC from ELR_ELx
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* no change to exception level, execution state or stack pointer
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*/
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env->pstate |= PSTATE_IL;
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env->pc = env->elr_el[cur_el];
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spsr &= PSTATE_NZCV | PSTATE_DAIF;
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spsr |= pstate_read(env) & ~(PSTATE_NZCV | PSTATE_DAIF);
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pstate_write(env, spsr);
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if (!arm_singlestep_active(env)) {
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env->pstate &= ~PSTATE_SS;
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}
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}
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/* Return true if the linked breakpoint entry lbn passes its checks */
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static bool linked_bp_matches(ARMCPU *cpu, int lbn)
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{
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CPUARMState *env = &cpu->env;
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uint64_t bcr = env->cp15.dbgbcr[lbn];
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int brps = extract32(cpu->dbgdidr, 24, 4);
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int ctx_cmps = extract32(cpu->dbgdidr, 20, 4);
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int bt;
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uint32_t contextidr;
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/* Links to unimplemented or non-context aware breakpoints are
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* CONSTRAINED UNPREDICTABLE: either behave as if disabled, or
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* as if linked to an UNKNOWN context-aware breakpoint (in which
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* case DBGWCR<n>_EL1.LBN must indicate that breakpoint).
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* We choose the former.
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*/
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if (lbn > brps || lbn < (brps - ctx_cmps)) {
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return false;
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}
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bcr = env->cp15.dbgbcr[lbn];
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if (extract64(bcr, 0, 1) == 0) {
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/* Linked breakpoint disabled : generate no events */
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return false;
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}
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bt = extract64(bcr, 20, 4);
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/* We match the whole register even if this is AArch32 using the
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* short descriptor format (in which case it holds both PROCID and ASID),
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* since we don't implement the optional v7 context ID masking.
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*/
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contextidr = extract64(env->cp15.contextidr_el1, 0, 32);
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switch (bt) {
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case 3: /* linked context ID match */
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if (arm_current_pl(env) > 1) {
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/* Context matches never fire in EL2 or (AArch64) EL3 */
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return false;
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}
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return (contextidr == extract64(env->cp15.dbgbvr[lbn], 0, 32));
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case 5: /* linked address mismatch (reserved in AArch64) */
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case 9: /* linked VMID match (reserved if no EL2) */
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case 11: /* linked context ID and VMID match (reserved if no EL2) */
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default:
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/* Links to Unlinked context breakpoints must generate no
|
|
* events; we choose to do the same for reserved values too.
|
|
*/
|
|
return false;
|
|
}
|
|
|
|
return false;
|
|
}
|
|
|
|
static bool wp_matches(ARMCPU *cpu, int n)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
uint64_t wcr = env->cp15.dbgwcr[n];
|
|
int pac, hmc, ssc, wt, lbn;
|
|
/* TODO: check against CPU security state when we implement TrustZone */
|
|
bool is_secure = false;
|
|
|
|
if (!env->cpu_watchpoint[n]
|
|
|| !(env->cpu_watchpoint[n]->flags & BP_WATCHPOINT_HIT)) {
|
|
return false;
|
|
}
|
|
|
|
/* The WATCHPOINT_HIT flag guarantees us that the watchpoint is
|
|
* enabled and that the address and access type match; check the
|
|
* remaining fields, including linked breakpoints.
|
|
* Note that some combinations of {PAC, HMC SSC} are reserved and
|
|
* must act either like some valid combination or as if the watchpoint
|
|
* were disabled. We choose the former, and use this together with
|
|
* the fact that EL3 must always be Secure and EL2 must always be
|
|
* Non-Secure to simplify the code slightly compared to the full
|
|
* table in the ARM ARM.
|
|
*/
|
|
pac = extract64(wcr, 1, 2);
|
|
hmc = extract64(wcr, 13, 1);
|
|
ssc = extract64(wcr, 14, 2);
|
|
|
|
switch (ssc) {
|
|
case 0:
|
|
break;
|
|
case 1:
|
|
case 3:
|
|
if (is_secure) {
|
|
return false;
|
|
}
|
|
break;
|
|
case 2:
|
|
if (!is_secure) {
|
|
return false;
|
|
}
|
|
break;
|
|
}
|
|
|
|
/* TODO: this is not strictly correct because the LDRT/STRT/LDT/STT
|
|
* "unprivileged access" instructions should match watchpoints as if
|
|
* they were accesses done at EL0, even if the CPU is at EL1 or higher.
|
|
* Implementing this would require reworking the core watchpoint code
|
|
* to plumb the mmu_idx through to this point. Luckily Linux does not
|
|
* rely on this behaviour currently.
|
|
*/
|
|
switch (arm_current_pl(env)) {
|
|
case 3:
|
|
case 2:
|
|
if (!hmc) {
|
|
return false;
|
|
}
|
|
break;
|
|
case 1:
|
|
if (extract32(pac, 0, 1) == 0) {
|
|
return false;
|
|
}
|
|
break;
|
|
case 0:
|
|
if (extract32(pac, 1, 1) == 0) {
|
|
return false;
|
|
}
|
|
break;
|
|
default:
|
|
g_assert_not_reached();
|
|
}
|
|
|
|
wt = extract64(wcr, 20, 1);
|
|
lbn = extract64(wcr, 16, 4);
|
|
|
|
if (wt && !linked_bp_matches(cpu, lbn)) {
|
|
return false;
|
|
}
|
|
|
|
return true;
|
|
}
|
|
|
|
static bool check_watchpoints(ARMCPU *cpu)
|
|
{
|
|
CPUARMState *env = &cpu->env;
|
|
int n;
|
|
|
|
/* If watchpoints are disabled globally or we can't take debug
|
|
* exceptions here then watchpoint firings are ignored.
|
|
*/
|
|
if (extract32(env->cp15.mdscr_el1, 15, 1) == 0
|
|
|| !arm_generate_debug_exceptions(env)) {
|
|
return false;
|
|
}
|
|
|
|
for (n = 0; n < ARRAY_SIZE(env->cpu_watchpoint); n++) {
|
|
if (wp_matches(cpu, n)) {
|
|
return true;
|
|
}
|
|
}
|
|
return false;
|
|
}
|
|
|
|
void arm_debug_excp_handler(CPUState *cs)
|
|
{
|
|
/* Called by core code when a watchpoint or breakpoint fires;
|
|
* need to check which one and raise the appropriate exception.
|
|
*/
|
|
ARMCPU *cpu = ARM_CPU(cs);
|
|
CPUARMState *env = &cpu->env;
|
|
CPUWatchpoint *wp_hit = cs->watchpoint_hit;
|
|
|
|
if (wp_hit) {
|
|
if (wp_hit->flags & BP_CPU) {
|
|
cs->watchpoint_hit = NULL;
|
|
if (check_watchpoints(cpu)) {
|
|
bool wnr = (wp_hit->flags & BP_WATCHPOINT_HIT_WRITE) != 0;
|
|
bool same_el = arm_debug_target_el(env) == arm_current_pl(env);
|
|
|
|
env->exception.syndrome = syn_watchpoint(same_el, 0, wnr);
|
|
if (extended_addresses_enabled(env)) {
|
|
env->exception.fsr = (1 << 9) | 0x22;
|
|
} else {
|
|
env->exception.fsr = 0x2;
|
|
}
|
|
env->exception.vaddress = wp_hit->hitaddr;
|
|
raise_exception(env, EXCP_DATA_ABORT);
|
|
} else {
|
|
cpu_resume_from_signal(cs, NULL);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/* ??? Flag setting arithmetic is awkward because we need to do comparisons.
|
|
The only way to do that in TCG is a conditional branch, which clobbers
|
|
all our temporaries. For now implement these as helper functions. */
|
|
|
|
/* Similarly for variable shift instructions. */
|
|
|
|
uint32_t HELPER(shl_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift = i & 0xff;
|
|
if (shift >= 32) {
|
|
if (shift == 32)
|
|
env->CF = x & 1;
|
|
else
|
|
env->CF = 0;
|
|
return 0;
|
|
} else if (shift != 0) {
|
|
env->CF = (x >> (32 - shift)) & 1;
|
|
return x << shift;
|
|
}
|
|
return x;
|
|
}
|
|
|
|
uint32_t HELPER(shr_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift = i & 0xff;
|
|
if (shift >= 32) {
|
|
if (shift == 32)
|
|
env->CF = (x >> 31) & 1;
|
|
else
|
|
env->CF = 0;
|
|
return 0;
|
|
} else if (shift != 0) {
|
|
env->CF = (x >> (shift - 1)) & 1;
|
|
return x >> shift;
|
|
}
|
|
return x;
|
|
}
|
|
|
|
uint32_t HELPER(sar_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift = i & 0xff;
|
|
if (shift >= 32) {
|
|
env->CF = (x >> 31) & 1;
|
|
return (int32_t)x >> 31;
|
|
} else if (shift != 0) {
|
|
env->CF = (x >> (shift - 1)) & 1;
|
|
return (int32_t)x >> shift;
|
|
}
|
|
return x;
|
|
}
|
|
|
|
uint32_t HELPER(ror_cc)(CPUARMState *env, uint32_t x, uint32_t i)
|
|
{
|
|
int shift1, shift;
|
|
shift1 = i & 0xff;
|
|
shift = shift1 & 0x1f;
|
|
if (shift == 0) {
|
|
if (shift1 != 0)
|
|
env->CF = (x >> 31) & 1;
|
|
return x;
|
|
} else {
|
|
env->CF = (x >> (shift - 1)) & 1;
|
|
return ((uint32_t)x >> shift) | (x << (32 - shift));
|
|
}
|
|
}
|