363 lines
10 KiB
C
363 lines
10 KiB
C
/*
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* QEMU 8253/8254 interval timer emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h"
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#include "pc.h"
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#include "isa.h"
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#include "qemu/timer.h"
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#include "i8254.h"
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#include "i8254_internal.h"
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//#define DEBUG_PIT
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#define RW_STATE_LSB 1
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#define RW_STATE_MSB 2
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#define RW_STATE_WORD0 3
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#define RW_STATE_WORD1 4
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time);
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static int pit_get_count(PITChannelState *s)
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{
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uint64_t d;
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int counter;
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d = muldiv64(qemu_get_clock_ns(vm_clock) - s->count_load_time, PIT_FREQ,
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get_ticks_per_sec());
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switch(s->mode) {
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case 0:
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case 1:
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case 4:
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case 5:
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counter = (s->count - d) & 0xffff;
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break;
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case 3:
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/* XXX: may be incorrect for odd counts */
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counter = s->count - ((2 * d) % s->count);
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break;
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default:
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counter = s->count - (d % s->count);
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break;
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}
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return counter;
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}
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/* val must be 0 or 1 */
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static void pit_set_channel_gate(PITCommonState *s, PITChannelState *sc,
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int val)
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{
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switch (sc->mode) {
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default:
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case 0:
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case 4:
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/* XXX: just disable/enable counting */
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break;
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case 1:
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case 5:
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if (sc->gate < val) {
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/* restart counting on rising edge */
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sc->count_load_time = qemu_get_clock_ns(vm_clock);
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pit_irq_timer_update(sc, sc->count_load_time);
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}
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break;
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case 2:
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case 3:
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if (sc->gate < val) {
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/* restart counting on rising edge */
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sc->count_load_time = qemu_get_clock_ns(vm_clock);
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pit_irq_timer_update(sc, sc->count_load_time);
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}
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/* XXX: disable/enable counting */
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break;
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}
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sc->gate = val;
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}
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static inline void pit_load_count(PITChannelState *s, int val)
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{
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if (val == 0)
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val = 0x10000;
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s->count_load_time = qemu_get_clock_ns(vm_clock);
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s->count = val;
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pit_irq_timer_update(s, s->count_load_time);
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}
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/* if already latched, do not latch again */
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static void pit_latch_count(PITChannelState *s)
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{
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if (!s->count_latched) {
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s->latched_count = pit_get_count(s);
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s->count_latched = s->rw_mode;
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}
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}
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static void pit_ioport_write(void *opaque, hwaddr addr,
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uint64_t val, unsigned size)
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{
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PITCommonState *pit = opaque;
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int channel, access;
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PITChannelState *s;
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addr &= 3;
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if (addr == 3) {
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channel = val >> 6;
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if (channel == 3) {
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/* read back command */
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for(channel = 0; channel < 3; channel++) {
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s = &pit->channels[channel];
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if (val & (2 << channel)) {
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if (!(val & 0x20)) {
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pit_latch_count(s);
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}
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if (!(val & 0x10) && !s->status_latched) {
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/* status latch */
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/* XXX: add BCD and null count */
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s->status =
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(pit_get_out(s,
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qemu_get_clock_ns(vm_clock)) << 7) |
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(s->rw_mode << 4) |
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(s->mode << 1) |
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s->bcd;
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s->status_latched = 1;
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}
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}
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}
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} else {
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s = &pit->channels[channel];
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access = (val >> 4) & 3;
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if (access == 0) {
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pit_latch_count(s);
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} else {
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s->rw_mode = access;
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s->read_state = access;
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s->write_state = access;
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s->mode = (val >> 1) & 7;
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s->bcd = val & 1;
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/* XXX: update irq timer ? */
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}
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}
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} else {
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s = &pit->channels[addr];
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switch(s->write_state) {
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default:
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case RW_STATE_LSB:
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pit_load_count(s, val);
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break;
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case RW_STATE_MSB:
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pit_load_count(s, val << 8);
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break;
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case RW_STATE_WORD0:
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s->write_latch = val;
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s->write_state = RW_STATE_WORD1;
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break;
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case RW_STATE_WORD1:
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pit_load_count(s, s->write_latch | (val << 8));
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s->write_state = RW_STATE_WORD0;
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break;
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}
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}
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}
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static uint64_t pit_ioport_read(void *opaque, hwaddr addr,
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unsigned size)
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{
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PITCommonState *pit = opaque;
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int ret, count;
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PITChannelState *s;
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addr &= 3;
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s = &pit->channels[addr];
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if (s->status_latched) {
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s->status_latched = 0;
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ret = s->status;
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} else if (s->count_latched) {
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switch(s->count_latched) {
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default:
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case RW_STATE_LSB:
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ret = s->latched_count & 0xff;
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s->count_latched = 0;
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break;
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case RW_STATE_MSB:
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ret = s->latched_count >> 8;
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s->count_latched = 0;
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break;
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case RW_STATE_WORD0:
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ret = s->latched_count & 0xff;
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s->count_latched = RW_STATE_MSB;
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break;
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}
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} else {
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switch(s->read_state) {
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default:
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case RW_STATE_LSB:
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count = pit_get_count(s);
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ret = count & 0xff;
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break;
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case RW_STATE_MSB:
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count = pit_get_count(s);
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ret = (count >> 8) & 0xff;
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break;
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case RW_STATE_WORD0:
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count = pit_get_count(s);
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ret = count & 0xff;
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s->read_state = RW_STATE_WORD1;
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break;
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case RW_STATE_WORD1:
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count = pit_get_count(s);
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ret = (count >> 8) & 0xff;
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s->read_state = RW_STATE_WORD0;
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break;
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}
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}
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return ret;
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}
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static void pit_irq_timer_update(PITChannelState *s, int64_t current_time)
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{
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int64_t expire_time;
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int irq_level;
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if (!s->irq_timer || s->irq_disabled) {
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return;
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}
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expire_time = pit_get_next_transition_time(s, current_time);
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irq_level = pit_get_out(s, current_time);
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qemu_set_irq(s->irq, irq_level);
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#ifdef DEBUG_PIT
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printf("irq_level=%d next_delay=%f\n",
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irq_level,
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(double)(expire_time - current_time) / get_ticks_per_sec());
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#endif
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s->next_transition_time = expire_time;
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if (expire_time != -1)
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qemu_mod_timer(s->irq_timer, expire_time);
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else
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qemu_del_timer(s->irq_timer);
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}
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static void pit_irq_timer(void *opaque)
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{
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PITChannelState *s = opaque;
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pit_irq_timer_update(s, s->next_transition_time);
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}
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static void pit_reset(DeviceState *dev)
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{
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PITCommonState *pit = DO_UPCAST(PITCommonState, dev.qdev, dev);
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PITChannelState *s;
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pit_reset_common(pit);
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s = &pit->channels[0];
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if (!s->irq_disabled) {
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qemu_mod_timer(s->irq_timer, s->next_transition_time);
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}
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}
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/* When HPET is operating in legacy mode, suppress the ignored timer IRQ,
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* reenable it when legacy mode is left again. */
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static void pit_irq_control(void *opaque, int n, int enable)
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{
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PITCommonState *pit = opaque;
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PITChannelState *s = &pit->channels[0];
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if (enable) {
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s->irq_disabled = 0;
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pit_irq_timer_update(s, qemu_get_clock_ns(vm_clock));
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} else {
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s->irq_disabled = 1;
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qemu_del_timer(s->irq_timer);
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}
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}
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static const MemoryRegionOps pit_ioport_ops = {
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.read = pit_ioport_read,
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.write = pit_ioport_write,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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.endianness = DEVICE_LITTLE_ENDIAN,
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};
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static void pit_post_load(PITCommonState *s)
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{
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PITChannelState *sc = &s->channels[0];
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if (sc->next_transition_time != -1) {
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qemu_mod_timer(sc->irq_timer, sc->next_transition_time);
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} else {
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qemu_del_timer(sc->irq_timer);
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}
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}
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static int pit_initfn(PITCommonState *pit)
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{
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PITChannelState *s;
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s = &pit->channels[0];
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/* the timer 0 is connected to an IRQ */
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s->irq_timer = qemu_new_timer_ns(vm_clock, pit_irq_timer, s);
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qdev_init_gpio_out(&pit->dev.qdev, &s->irq, 1);
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memory_region_init_io(&pit->ioports, &pit_ioport_ops, pit, "pit", 4);
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qdev_init_gpio_in(&pit->dev.qdev, pit_irq_control, 1);
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return 0;
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}
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static Property pit_properties[] = {
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DEFINE_PROP_HEX32("iobase", PITCommonState, iobase, -1),
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DEFINE_PROP_END_OF_LIST(),
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};
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static void pit_class_initfn(ObjectClass *klass, void *data)
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{
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PITCommonClass *k = PIT_COMMON_CLASS(klass);
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DeviceClass *dc = DEVICE_CLASS(klass);
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k->init = pit_initfn;
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k->set_channel_gate = pit_set_channel_gate;
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k->get_channel_info = pit_get_channel_info_common;
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k->post_load = pit_post_load;
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dc->reset = pit_reset;
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dc->props = pit_properties;
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}
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static TypeInfo pit_info = {
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.name = "isa-pit",
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.parent = TYPE_PIT_COMMON,
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.instance_size = sizeof(PITCommonState),
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.class_init = pit_class_initfn,
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};
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static void pit_register_types(void)
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{
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type_register_static(&pit_info);
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}
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type_init(pit_register_types)
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