ce3af0bbbc
Add encode, trans* functions and helper functions support for Zcmt instrutions. Add support for jvt csr. Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn> Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20230307081403.61950-8-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
229 lines
9.0 KiB
Plaintext
229 lines
9.0 KiB
Plaintext
#
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# RISC-V translation routines for the RVXI Base Integer Instruction Set.
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#
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# Copyright (c) 2018 Peer Adelt, peer.adelt@hni.uni-paderborn.de
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# Bastian Koppelmann, kbastian@mail.uni-paderborn.de
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#
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# This program is free software; you can redistribute it and/or modify it
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# under the terms and conditions of the GNU General Public License,
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# version 2 or later, as published by the Free Software Foundation.
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#
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# This program is distributed in the hope it will be useful, but WITHOUT
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# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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# more details.
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#
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# You should have received a copy of the GNU General Public License along with
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# this program. If not, see <http://www.gnu.org/licenses/>.
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# Fields:
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%rd 7:5
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%rs1_3 7:3 !function=ex_rvc_register
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%rs2_3 2:3 !function=ex_rvc_register
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%rs2_5 2:5
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%r1s 7:3 !function=ex_sreg_register
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%r2s 2:3 !function=ex_sreg_register
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# Immediates:
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%imm_ci 12:s1 2:5
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%nzuimm_ciw 7:4 11:2 5:1 6:1 !function=ex_shift_2
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%uimm_cl_q 10:1 5:2 11:2 !function=ex_shift_4
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%uimm_cl_d 5:2 10:3 !function=ex_shift_3
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%uimm_cl_w 5:1 10:3 6:1 !function=ex_shift_2
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%imm_cb 12:s1 5:2 2:1 10:2 3:2 !function=ex_shift_1
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%imm_cj 12:s1 8:1 9:2 6:1 7:1 2:1 11:1 3:3 !function=ex_shift_1
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%shlimm_6bit 12:1 2:5 !function=ex_rvc_shiftli
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%shrimm_6bit 12:1 2:5 !function=ex_rvc_shiftri
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%uimm_6bit_lq 2:4 12:1 6:1 !function=ex_shift_4
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%uimm_6bit_ld 2:3 12:1 5:2 !function=ex_shift_3
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%uimm_6bit_lw 2:2 12:1 4:3 !function=ex_shift_2
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%uimm_6bit_sq 7:4 11:2 !function=ex_shift_4
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%uimm_6bit_sd 7:3 10:3 !function=ex_shift_3
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%uimm_6bit_sw 7:2 9:4 !function=ex_shift_2
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%imm_addi16sp 12:s1 3:2 5:1 2:1 6:1 !function=ex_shift_4
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%imm_lui 12:s1 2:5 !function=ex_shift_12
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%uimm_cl_b 5:1 6:1
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%uimm_cl_h 5:1 !function=ex_shift_1
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%spimm 2:2 !function=ex_shift_4
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%urlist 4:4
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%index 2:8
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# Argument sets imported from insn32.decode:
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&empty !extern
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&r rd rs1 rs2 !extern
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&i imm rs1 rd !extern
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&s imm rs1 rs2 !extern
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&j imm rd !extern
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&b imm rs2 rs1 !extern
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&u imm rd !extern
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&shift shamt rs1 rd !extern
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&r2 rd rs1 !extern
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&r2_s rs1 rs2 !extern
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&cmpp urlist spimm
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&cmjt index
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# Formats 16:
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@cr .... ..... ..... .. &r rs2=%rs2_5 rs1=%rd %rd
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@ci ... . ..... ..... .. &i imm=%imm_ci rs1=%rd %rd
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@cl_q ... . ..... ..... .. &i imm=%uimm_cl_q rs1=%rs1_3 rd=%rs2_3
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@cl_d ... ... ... .. ... .. &i imm=%uimm_cl_d rs1=%rs1_3 rd=%rs2_3
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@cl_w ... ... ... .. ... .. &i imm=%uimm_cl_w rs1=%rs1_3 rd=%rs2_3
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@cs_2 ... ... ... .. ... .. &r rs2=%rs2_3 rs1=%rs1_3 rd=%rs1_3
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@cs_q ... ... ... .. ... .. &s imm=%uimm_cl_q rs1=%rs1_3 rs2=%rs2_3
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@cs_d ... ... ... .. ... .. &s imm=%uimm_cl_d rs1=%rs1_3 rs2=%rs2_3
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@cs_w ... ... ... .. ... .. &s imm=%uimm_cl_w rs1=%rs1_3 rs2=%rs2_3
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@cj ... ........... .. &j imm=%imm_cj
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@cb_z ... ... ... .. ... .. &b imm=%imm_cb rs1=%rs1_3 rs2=0
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@c_lqsp ... . ..... ..... .. &i imm=%uimm_6bit_lq rs1=2 %rd
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@c_ldsp ... . ..... ..... .. &i imm=%uimm_6bit_ld rs1=2 %rd
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@c_lwsp ... . ..... ..... .. &i imm=%uimm_6bit_lw rs1=2 %rd
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@c_sqsp ... . ..... ..... .. &s imm=%uimm_6bit_sq rs1=2 rs2=%rs2_5
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@c_sdsp ... . ..... ..... .. &s imm=%uimm_6bit_sd rs1=2 rs2=%rs2_5
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@c_swsp ... . ..... ..... .. &s imm=%uimm_6bit_sw rs1=2 rs2=%rs2_5
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@c_li ... . ..... ..... .. &i imm=%imm_ci rs1=0 %rd
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@c_lui ... . ..... ..... .. &u imm=%imm_lui %rd
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@c_jalr ... . ..... ..... .. &i imm=0 rs1=%rd
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@c_mv ... . ..... ..... .. &i imm=0 rs1=%rs2_5 %rd
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@c_addi4spn ... . ..... ..... .. &i imm=%nzuimm_ciw rs1=2 rd=%rs2_3
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@c_addi16sp ... . ..... ..... .. &i imm=%imm_addi16sp rs1=2 rd=2
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@c_shift ... . .. ... ..... .. \
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&shift rd=%rs1_3 rs1=%rs1_3 shamt=%shrimm_6bit
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@c_shift2 ... . .. ... ..... .. \
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&shift rd=%rd rs1=%rd shamt=%shlimm_6bit
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@c_andi ... . .. ... ..... .. &i imm=%imm_ci rs1=%rs1_3 rd=%rs1_3
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@cu ... ... ... .. ... .. &r2 rs1=%rs1_3 rd=%rs1_3
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@cl_b ... . .. ... .. ... .. &i imm=%uimm_cl_b rs1=%rs1_3 rd=%rs2_3
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@cl_h ... . .. ... .. ... .. &i imm=%uimm_cl_h rs1=%rs1_3 rd=%rs2_3
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@cs_b ... . .. ... .. ... .. &s imm=%uimm_cl_b rs1=%rs1_3 rs2=%rs2_3
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@cs_h ... . .. ... .. ... .. &s imm=%uimm_cl_h rs1=%rs1_3 rs2=%rs2_3
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@cm_pp ... ... ........ .. &cmpp %urlist %spimm
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@cm_mv ... ... ... .. ... .. &r2_s rs2=%r2s rs1=%r1s
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@cm_jt ... ... ........ .. &cmjt %index
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# *** RV32/64C Standard Extension (Quadrant 0) ***
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{
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# Opcode of all zeros is illegal; rd != 0, nzuimm == 0 is reserved.
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illegal 000 000 000 00 --- 00
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addi 000 ... ... .. ... 00 @c_addi4spn
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}
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{
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lq 001 ... ... .. ... 00 @cl_q
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c_fld 001 ... ... .. ... 00 @cl_d
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}
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lw 010 ... ... .. ... 00 @cl_w
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{
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sq 101 ... ... .. ... 00 @cs_q
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c_fsd 101 ... ... .. ... 00 @cs_d
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}
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sw 110 ... ... .. ... 00 @cs_w
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# *** RV32C and RV64C specific Standard Extension (Quadrant 0) ***
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{
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ld 011 ... ... .. ... 00 @cl_d
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c_flw 011 ... ... .. ... 00 @cl_w
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}
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{
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sd 111 ... ... .. ... 00 @cs_d
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c_fsw 111 ... ... .. ... 00 @cs_w
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}
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# *** RV32/64C Standard Extension (Quadrant 1) ***
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addi 000 . ..... ..... 01 @ci
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addi 010 . ..... ..... 01 @c_li
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{
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illegal 011 0 ----- 00000 01 # c.addi16sp and c.lui, RES nzimm=0
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addi 011 . 00010 ..... 01 @c_addi16sp
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lui 011 . ..... ..... 01 @c_lui
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}
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srli 100 . 00 ... ..... 01 @c_shift
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srai 100 . 01 ... ..... 01 @c_shift
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andi 100 . 10 ... ..... 01 @c_andi
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sub 100 0 11 ... 00 ... 01 @cs_2
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xor 100 0 11 ... 01 ... 01 @cs_2
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or 100 0 11 ... 10 ... 01 @cs_2
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and 100 0 11 ... 11 ... 01 @cs_2
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jal 101 ........... 01 @cj rd=0 # C.J
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beq 110 ... ... ..... 01 @cb_z
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bne 111 ... ... ..... 01 @cb_z
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# *** RV64C and RV32C specific Standard Extension (Quadrant 1) ***
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{
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c64_illegal 001 - 00000 ----- 01 # c.addiw, RES rd=0
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addiw 001 . ..... ..... 01 @ci
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jal 001 ........... 01 @cj rd=1 # C.JAL
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}
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subw 100 1 11 ... 00 ... 01 @cs_2
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addw 100 1 11 ... 01 ... 01 @cs_2
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# *** RV32/64C Standard Extension (Quadrant 2) ***
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slli 000 . ..... ..... 10 @c_shift2
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{
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lq 001 ... ... .. ... 10 @c_lqsp
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c_fld 001 . ..... ..... 10 @c_ldsp
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}
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{
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illegal 010 - 00000 ----- 10 # c.lwsp, RES rd=0
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lw 010 . ..... ..... 10 @c_lwsp
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}
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{
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illegal 100 0 00000 00000 10 # c.jr, RES rs1=0
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jalr 100 0 ..... 00000 10 @c_jalr rd=0 # C.JR
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addi 100 0 ..... ..... 10 @c_mv
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}
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{
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ebreak 100 1 00000 00000 10
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jalr 100 1 ..... 00000 10 @c_jalr rd=1 # C.JALR
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add 100 1 ..... ..... 10 @cr
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}
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{
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sq 101 ... ... .. ... 10 @c_sqsp
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c_fsd 101 ...... ..... 10 @c_sdsp
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# *** RV64 and RV32 Zcmp/Zcmt Extension ***
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[
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cm_push 101 11000 .... .. 10 @cm_pp
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cm_pop 101 11010 .... .. 10 @cm_pp
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cm_popret 101 11110 .... .. 10 @cm_pp
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cm_popretz 101 11100 .... .. 10 @cm_pp
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cm_mva01s 101 011 ... 11 ... 10 @cm_mv
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cm_mvsa01 101 011 ... 01 ... 10 @cm_mv
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cm_jalt 101 000 ........ 10 @cm_jt
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]
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}
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sw 110 . ..... ..... 10 @c_swsp
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# *** RV32C and RV64C specific Standard Extension (Quadrant 2) ***
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{
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c64_illegal 011 - 00000 ----- 10 # c.ldsp, RES rd=0
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ld 011 . ..... ..... 10 @c_ldsp
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c_flw 011 . ..... ..... 10 @c_lwsp
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}
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{
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sd 111 . ..... ..... 10 @c_sdsp
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c_fsw 111 . ..... ..... 10 @c_swsp
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}
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# *** RV64 and RV32 Zcb Extension ***
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c_zext_b 100 111 ... 11 000 01 @cu
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c_sext_b 100 111 ... 11 001 01 @cu
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c_zext_h 100 111 ... 11 010 01 @cu
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c_sext_h 100 111 ... 11 011 01 @cu
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c_zext_w 100 111 ... 11 100 01 @cu
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c_not 100 111 ... 11 101 01 @cu
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c_mul 100 111 ... 10 ... 01 @cs_2
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c_lbu 100 000 ... .. ... 00 @cl_b
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c_lhu 100 001 ... 0. ... 00 @cl_h
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c_lh 100 001 ... 1. ... 00 @cl_h
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c_sb 100 010 ... .. ... 00 @cs_b
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c_sh 100 011 ... 0. ... 00 @cs_h
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