774204cf98
This commit adds support for x2APIC transitions when writing to MSR_IA32_APICBASE register and finally adds CPUID_EXT_X2APIC to TCG_EXT_FEATURES. The set_base in APICCommonClass now returns an integer to indicate error in execution. apic_set_base return -1 on invalid APIC state transition, accelerator can use this to raise appropriate exception. Signed-off-by: Bui Quang Minh <minhquangbui99@gmail.com> Message-Id: <20240111154404.5333-4-minhquangbui99@gmail.com> Acked-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
234 lines
7.9 KiB
C
234 lines
7.9 KiB
C
/*
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* APIC support - internal interfaces
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*
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* Copyright (c) 2004-2005 Fabrice Bellard
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* Copyright (c) 2011 Jan Kiszka, Siemens AG
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>
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*/
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#ifndef QEMU_APIC_INTERNAL_H
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#define QEMU_APIC_INTERNAL_H
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#include "cpu.h"
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#include "exec/memory.h"
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#include "qemu/timer.h"
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#include "target/i386/cpu-qom.h"
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#include "qom/object.h"
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/* APIC Local Vector Table */
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#define APIC_LVT_TIMER 0
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#define APIC_LVT_THERMAL 1
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#define APIC_LVT_PERFORM 2
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#define APIC_LVT_LINT0 3
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#define APIC_LVT_LINT1 4
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#define APIC_LVT_ERROR 5
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#define APIC_LVT_NB 6
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/* APIC delivery modes */
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#define APIC_DM_FIXED 0
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#define APIC_DM_LOWPRI 1
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#define APIC_DM_SMI 2
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#define APIC_DM_NMI 4
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#define APIC_DM_INIT 5
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#define APIC_DM_SIPI 6
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#define APIC_DM_EXTINT 7
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/* APIC destination mode */
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#define APIC_DESTMODE_PHYSICAL 0
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#define APIC_DESTMODE_LOGICAL 1
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#define APIC_DESTMODE_LOGICAL_FLAT 0xf
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#define APIC_DESTMODE_LOGICAL_CLUSTER 0
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#define APIC_TRIGGER_EDGE 0
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#define APIC_TRIGGER_LEVEL 1
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#define APIC_VECTOR_MASK 0xff
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#define APIC_DCR_MASK 0xf
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#define APIC_LVT_TIMER_SHIFT 17
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#define APIC_LVT_MASKED_SHIFT 16
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#define APIC_LVT_LEVEL_TRIGGER_SHIFT 15
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#define APIC_LVT_REMOTE_IRR_SHIFT 14
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#define APIC_LVT_INT_POLARITY_SHIFT 13
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#define APIC_LVT_DELIV_STS_SHIFT 12
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#define APIC_LVT_DELIV_MOD_SHIFT 8
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#define APIC_LVT_TIMER_TSCDEADLINE (2 << APIC_LVT_TIMER_SHIFT)
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#define APIC_LVT_TIMER_PERIODIC (1 << APIC_LVT_TIMER_SHIFT)
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#define APIC_LVT_MASKED (1 << APIC_LVT_MASKED_SHIFT)
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#define APIC_LVT_LEVEL_TRIGGER (1 << APIC_LVT_LEVEL_TRIGGER_SHIFT)
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#define APIC_LVT_REMOTE_IRR (1 << APIC_LVT_REMOTE_IRR_SHIFT)
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#define APIC_LVT_INT_POLARITY (1 << APIC_LVT_INT_POLARITY_SHIFT)
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#define APIC_LVT_DELIV_STS (1 << APIC_LVT_DELIV_STS_SHIFT)
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#define APIC_LVT_DELIV_MOD (7 << APIC_LVT_DELIV_MOD_SHIFT)
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#define APIC_ESR_ILL_ADDRESS_SHIFT 7
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#define APIC_ESR_RECV_ILL_VECT_SHIFT 6
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#define APIC_ESR_SEND_ILL_VECT_SHIFT 5
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#define APIC_ESR_RECV_ACCEPT_SHIFT 3
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#define APIC_ESR_SEND_ACCEPT_SHIFT 2
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#define APIC_ESR_RECV_CHECK_SUM_SHIFT 1
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#define APIC_ESR_ILLEGAL_ADDRESS (1 << APIC_ESR_ILL_ADDRESS_SHIFT)
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#define APIC_ESR_RECV_ILLEGAL_VECT (1 << APIC_ESR_RECV_ILL_VECT_SHIFT)
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#define APIC_ESR_SEND_ILLEGAL_VECT (1 << APIC_ESR_SEND_ILL_VECT_SHIFT)
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#define APIC_ESR_RECV_ACCEPT (1 << APIC_ESR_RECV_ACCEPT_SHIFT)
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#define APIC_ESR_SEND_ACCEPT (1 << APIC_ESR_SEND_ACCEPT_SHIFT)
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#define APIC_ESR_RECV_CHECK_SUM (1 << APIC_ESR_RECV_CHECK_SUM_SHIFT)
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#define APIC_ESR_SEND_CHECK_SUM 1
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#define APIC_ICR_DEST_SHIFT 24
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#define APIC_ICR_DEST_SHORT_SHIFT 18
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#define APIC_ICR_TRIGGER_MOD_SHIFT 15
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#define APIC_ICR_LEVEL_SHIFT 14
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#define APIC_ICR_DELIV_STS_SHIFT 12
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#define APIC_ICR_DEST_MOD_SHIFT 11
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#define APIC_ICR_DELIV_MOD_SHIFT 8
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#define APIC_ICR_DEST_SHORT (3 << APIC_ICR_DEST_SHORT_SHIFT)
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#define APIC_ICR_TRIGGER_MOD (1 << APIC_ICR_TRIGGER_MOD_SHIFT)
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#define APIC_ICR_LEVEL (1 << APIC_ICR_LEVEL_SHIFT)
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#define APIC_ICR_DELIV_STS (1 << APIC_ICR_DELIV_STS_SHIFT)
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#define APIC_ICR_DEST_MOD (1 << APIC_ICR_DEST_MOD_SHIFT)
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#define APIC_ICR_DELIV_MOD (7 << APIC_ICR_DELIV_MOD_SHIFT)
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#define APIC_PR_CLASS_SHIFT 4
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#define APIC_PR_SUB_CLASS 0xf
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#define APIC_LOGDEST_XAPIC_SHIFT 4
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#define APIC_LOGDEST_XAPIC_ID 0xf
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#define APIC_LOGDEST_X2APIC_SHIFT 16
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#define APIC_LOGDEST_X2APIC_ID 0xffff
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#define APIC_SPURIO_FOCUS_SHIFT 9
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#define APIC_SPURIO_ENABLED_SHIFT 8
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#define APIC_SPURIO_FOCUS (1 << APIC_SPURIO_FOCUS_SHIFT)
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#define APIC_SPURIO_ENABLED (1 << APIC_SPURIO_ENABLED_SHIFT)
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#define APIC_SV_DIRECTED_IO (1 << 12)
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#define APIC_SV_ENABLE (1 << 8)
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#define VAPIC_ENABLE_BIT 0
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#define VAPIC_ENABLE_MASK (1 << VAPIC_ENABLE_BIT)
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typedef struct APICCommonState APICCommonState;
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#define TYPE_APIC_COMMON "apic-common"
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typedef struct APICCommonClass APICCommonClass;
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DECLARE_OBJ_CHECKERS(APICCommonState, APICCommonClass,
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APIC_COMMON, TYPE_APIC_COMMON)
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struct APICCommonClass {
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DeviceClass parent_class;
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DeviceRealize realize;
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DeviceUnrealize unrealize;
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int (*set_base)(APICCommonState *s, uint64_t val);
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void (*set_tpr)(APICCommonState *s, uint8_t val);
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uint8_t (*get_tpr)(APICCommonState *s);
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void (*enable_tpr_reporting)(APICCommonState *s, bool enable);
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void (*vapic_base_update)(APICCommonState *s);
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void (*external_nmi)(APICCommonState *s);
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void (*pre_save)(APICCommonState *s);
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void (*post_load)(APICCommonState *s);
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void (*reset)(APICCommonState *s);
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/* send_msi emulates an APIC bus and its proper place would be in a new
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* device, but it's convenient to have it here for now.
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*/
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void (*send_msi)(MSIMessage *msi);
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};
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struct APICCommonState {
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/*< private >*/
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DeviceState parent_obj;
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/*< public >*/
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MemoryRegion io_memory;
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X86CPU *cpu;
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uint32_t apicbase;
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uint8_t id; /* legacy APIC ID */
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uint32_t initial_apic_id;
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uint8_t version;
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uint8_t arb_id;
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uint8_t tpr;
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uint32_t spurious_vec;
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uint8_t log_dest;
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uint8_t dest_mode;
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uint32_t isr[8]; /* in service register */
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uint32_t tmr[8]; /* trigger mode register */
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uint32_t irr[8]; /* interrupt request register */
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uint32_t lvt[APIC_LVT_NB];
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uint32_t esr; /* error register */
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uint32_t icr[2];
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uint32_t divide_conf;
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int count_shift;
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uint32_t initial_count;
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int64_t initial_count_load_time;
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int64_t next_time;
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QEMUTimer *timer;
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int64_t timer_expiry;
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int sipi_vector;
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int wait_for_sipi;
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uint32_t vapic_control;
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DeviceState *vapic;
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hwaddr vapic_paddr; /* note: persistence via kvmvapic */
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bool legacy_instance_id;
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uint32_t extended_log_dest;
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};
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typedef struct VAPICState {
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uint8_t tpr;
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uint8_t isr;
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uint8_t zero;
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uint8_t irr;
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uint8_t enabled;
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} QEMU_PACKED VAPICState;
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extern bool apic_report_tpr_access;
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bool apic_next_timer(APICCommonState *s, int64_t current_time);
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void apic_enable_tpr_access_reporting(DeviceState *d, bool enable);
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void apic_enable_vapic(DeviceState *d, hwaddr paddr);
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void vapic_report_tpr_access(DeviceState *dev, CPUState *cpu, target_ulong ip,
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TPRAccess access);
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int apic_get_ppr(APICCommonState *s);
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uint32_t apic_get_current_count(APICCommonState *s);
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static inline void apic_set_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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tab[i] |= mask;
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}
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static inline int apic_get_bit(uint32_t *tab, int index)
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{
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int i, mask;
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i = index >> 5;
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mask = 1 << (index & 0x1f);
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return !!(tab[i] & mask);
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}
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APICCommonClass *apic_get_class(Error **errp);
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#endif /* QEMU_APIC_INTERNAL_H */
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