8fcc477d49
Correct typos automatically found with the `typos` tool <https://crates.io/crates/typos> Signed-off-by: Manos Pitsidianakis <manos.pitsidianakis@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru> Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>
344 lines
11 KiB
C
344 lines
11 KiB
C
/*
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* Nuvoton NPCM7xx/8xx GMAC Module
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*
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* Copyright 2024 Google LLC
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* Authors:
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* Hao Wu <wuhaotsh@google.com>
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* Nabih Estefan <nabihestefan@google.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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* for more details.
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*/
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#ifndef NPCM_GMAC_H
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#define NPCM_GMAC_H
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#include "hw/irq.h"
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#include "hw/sysbus.h"
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#include "net/net.h"
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#define NPCM_GMAC_NR_REGS (0x1060 / sizeof(uint32_t))
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#define NPCM_GMAC_MAX_PHYS 32
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#define NPCM_GMAC_MAX_PHY_REGS 32
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struct NPCMGMACRxDesc {
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uint32_t rdes0;
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uint32_t rdes1;
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uint32_t rdes2;
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uint32_t rdes3;
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};
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/* NPCMGMACRxDesc.flags values */
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/* RDES2 and RDES3 are buffer addresses */
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/* Owner: 0 = software, 1 = dma */
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#define RX_DESC_RDES0_OWN BIT(31)
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/* Destination Address Filter Fail */
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#define RX_DESC_RDES0_DEST_ADDR_FILT_FAIL BIT(30)
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/* Frame length */
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#define RX_DESC_RDES0_FRAME_LEN_MASK(word) extract32(word, 16, 14)
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/* Frame length Shift*/
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#define RX_DESC_RDES0_FRAME_LEN_SHIFT 16
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/* Error Summary */
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#define RX_DESC_RDES0_ERR_SUMM_MASK BIT(15)
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/* Descriptor Error */
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#define RX_DESC_RDES0_DESC_ERR_MASK BIT(14)
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/* Source Address Filter Fail */
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#define RX_DESC_RDES0_SRC_ADDR_FILT_FAIL_MASK BIT(13)
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/* Length Error */
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#define RX_DESC_RDES0_LEN_ERR_MASK BIT(12)
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/* Overflow Error */
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#define RX_DESC_RDES0_OVRFLW_ERR_MASK BIT(11)
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/* VLAN Tag */
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#define RX_DESC_RDES0_VLAN_TAG_MASK BIT(10)
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/* First Descriptor */
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#define RX_DESC_RDES0_FIRST_DESC_MASK BIT(9)
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/* Last Descriptor */
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#define RX_DESC_RDES0_LAST_DESC_MASK BIT(8)
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/* IPC Checksum Error/Giant Frame */
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#define RX_DESC_RDES0_IPC_CHKSM_ERR_GNT_FRM_MASK BIT(7)
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/* Late Collision */
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#define RX_DESC_RDES0_LT_COLL_MASK BIT(6)
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/* Frame Type */
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#define RX_DESC_RDES0_FRM_TYPE_MASK BIT(5)
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/* Receive Watchdog Timeout */
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#define RX_DESC_RDES0_REC_WTCHDG_TMT_MASK BIT(4)
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/* Receive Error */
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#define RX_DESC_RDES0_RCV_ERR_MASK BIT(3)
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/* Dribble Bit Error */
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#define RX_DESC_RDES0_DRBL_BIT_ERR_MASK BIT(2)
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/* Cyclcic Redundancy Check Error */
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#define RX_DESC_RDES0_CRC_ERR_MASK BIT(1)
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/* Rx MAC Address/Payload Checksum Error */
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#define RC_DESC_RDES0_RCE_MASK BIT(0)
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/* Disable Interrupt on Completion */
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#define RX_DESC_RDES1_DIS_INTR_COMP_MASK BIT(31)
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/* Receive end of ring */
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#define RX_DESC_RDES1_RC_END_RING_MASK BIT(25)
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/* Second Address Chained */
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#define RX_DESC_RDES1_SEC_ADDR_CHND_MASK BIT(24)
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/* Receive Buffer 2 Size */
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#define RX_DESC_RDES1_BFFR2_SZ_SHIFT 11
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#define RX_DESC_RDES1_BFFR2_SZ_MASK(word) extract32(word, \
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RX_DESC_RDES1_BFFR2_SZ_SHIFT, 11)
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/* Receive Buffer 1 Size */
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#define RX_DESC_RDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11)
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struct NPCMGMACTxDesc {
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uint32_t tdes0;
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uint32_t tdes1;
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uint32_t tdes2;
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uint32_t tdes3;
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};
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/* NPCMGMACTxDesc.flags values */
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/* TDES2 and TDES3 are buffer addresses */
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/* Owner: 0 = software, 1 = gmac */
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#define TX_DESC_TDES0_OWN BIT(31)
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/* Tx Time Stamp Status */
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#define TX_DESC_TDES0_TTSS_MASK BIT(17)
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/* IP Header Error */
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#define TX_DESC_TDES0_IP_HEAD_ERR_MASK BIT(16)
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/* Error Summary */
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#define TX_DESC_TDES0_ERR_SUMM_MASK BIT(15)
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/* Jabber Timeout */
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#define TX_DESC_TDES0_JBBR_TMT_MASK BIT(14)
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/* Frame Flushed */
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#define TX_DESC_TDES0_FRM_FLSHD_MASK BIT(13)
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/* Payload Checksum Error */
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#define TX_DESC_TDES0_PYLD_CHKSM_ERR_MASK BIT(12)
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/* Loss of Carrier */
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#define TX_DESC_TDES0_LSS_CARR_MASK BIT(11)
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/* No Carrier */
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#define TX_DESC_TDES0_NO_CARR_MASK BIT(10)
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/* Late Collision */
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#define TX_DESC_TDES0_LATE_COLL_MASK BIT(9)
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/* Excessive Collision */
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#define TX_DESC_TDES0_EXCS_COLL_MASK BIT(8)
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/* VLAN Frame */
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#define TX_DESC_TDES0_VLAN_FRM_MASK BIT(7)
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/* Collision Count */
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#define TX_DESC_TDES0_COLL_CNT_MASK(word) extract32(word, 3, 4)
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/* Excessive Deferral */
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#define TX_DESC_TDES0_EXCS_DEF_MASK BIT(2)
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/* Underflow Error */
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#define TX_DESC_TDES0_UNDRFLW_ERR_MASK BIT(1)
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/* Deferred Bit */
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#define TX_DESC_TDES0_DFRD_BIT_MASK BIT(0)
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/* Interrupt of Completion */
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#define TX_DESC_TDES1_INTERR_COMP_MASK BIT(31)
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/* Last Segment */
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#define TX_DESC_TDES1_LAST_SEG_MASK BIT(30)
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/* First Segment */
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#define TX_DESC_TDES1_FIRST_SEG_MASK BIT(29)
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/* Checksum Insertion Control */
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#define TX_DESC_TDES1_CHKSM_INS_CTRL_MASK(word) extract32(word, 27, 2)
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/* Disable Cyclic Redundancy Check */
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#define TX_DESC_TDES1_DIS_CDC_MASK BIT(26)
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/* Transmit End of Ring */
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#define TX_DESC_TDES1_TX_END_RING_MASK BIT(25)
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/* Secondary Address Chained */
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#define TX_DESC_TDES1_SEC_ADDR_CHND_MASK BIT(24)
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/* Transmit Buffer 2 Size */
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#define TX_DESC_TDES1_BFFR2_SZ_MASK(word) extract32(word, 11, 11)
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/* Transmit Buffer 1 Size */
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#define TX_DESC_TDES1_BFFR1_SZ_MASK(word) extract32(word, 0, 11)
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typedef struct NPCMGMACState {
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SysBusDevice parent;
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MemoryRegion iomem;
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qemu_irq irq;
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NICState *nic;
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NICConf conf;
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uint32_t regs[NPCM_GMAC_NR_REGS];
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uint16_t phy_regs[NPCM_GMAC_MAX_PHYS][NPCM_GMAC_MAX_PHY_REGS];
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} NPCMGMACState;
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#define TYPE_NPCM_GMAC "npcm-gmac"
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OBJECT_DECLARE_SIMPLE_TYPE(NPCMGMACState, NPCM_GMAC)
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/* Mask for RO bits in Status */
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#define NPCM_DMA_STATUS_RO_MASK(word) (word & 0xfffe0000)
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/* Mask for RO bits in Status */
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#define NPCM_DMA_STATUS_W1C_MASK(word) (word & 0x1e7ff)
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/* Transmit Process State */
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#define NPCM_DMA_STATUS_TX_PROCESS_STATE_SHIFT 20
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/* Transmit States */
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#define NPCM_DMA_STATUS_TX_STOPPED_STATE \
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(0b000)
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#define NPCM_DMA_STATUS_TX_RUNNING_FETCHING_STATE \
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(0b001)
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#define NPCM_DMA_STATUS_TX_RUNNING_WAITING_STATE \
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(0b010)
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#define NPCM_DMA_STATUS_TX_RUNNING_READ_STATE \
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(0b011)
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#define NPCM_DMA_STATUS_TX_SUSPENDED_STATE \
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(0b110)
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#define NPCM_DMA_STATUS_TX_RUNNING_CLOSING_STATE \
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(0b111)
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/* Transmit Process State */
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#define NPCM_DMA_STATUS_RX_PROCESS_STATE_SHIFT 17
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/* Receive States */
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#define NPCM_DMA_STATUS_RX_STOPPED_STATE \
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(0b000)
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#define NPCM_DMA_STATUS_RX_RUNNING_FETCHING_STATE \
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(0b001)
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#define NPCM_DMA_STATUS_RX_RUNNING_WAITING_STATE \
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(0b011)
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#define NPCM_DMA_STATUS_RX_SUSPENDED_STATE \
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(0b100)
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#define NPCM_DMA_STATUS_RX_RUNNING_CLOSING_STATE \
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(0b101)
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#define NPCM_DMA_STATUS_RX_RUNNING_TRANSFERRING_STATE \
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(0b111)
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/* Early Receive Interrupt */
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#define NPCM_DMA_STATUS_ERI BIT(14)
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/* Fatal Bus Error Interrupt */
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#define NPCM_DMA_STATUS_FBI BIT(13)
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/* Early transmit Interrupt */
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#define NPCM_DMA_STATUS_ETI BIT(10)
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/* Receive Watchdog Timeout */
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#define NPCM_DMA_STATUS_RWT BIT(9)
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/* Receive Process Stopped */
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#define NPCM_DMA_STATUS_RPS BIT(8)
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/* Receive Buffer Unavailable */
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#define NPCM_DMA_STATUS_RU BIT(7)
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/* Receive Interrupt */
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#define NPCM_DMA_STATUS_RI BIT(6)
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/* Transmit Underflow */
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#define NPCM_DMA_STATUS_UNF BIT(5)
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/* Receive Overflow */
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#define NPCM_DMA_STATUS_OVF BIT(4)
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/* Transmit Jabber Timeout */
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#define NPCM_DMA_STATUS_TJT BIT(3)
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/* Transmit Buffer Unavailable */
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#define NPCM_DMA_STATUS_TU BIT(2)
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/* Transmit Process Stopped */
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#define NPCM_DMA_STATUS_TPS BIT(1)
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/* Transmit Interrupt */
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#define NPCM_DMA_STATUS_TI BIT(0)
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/* Normal Interrupt Summary */
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#define NPCM_DMA_STATUS_NIS BIT(16)
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/* Interrupts enabled by NIE */
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#define NPCM_DMA_STATUS_NIS_BITS (NPCM_DMA_STATUS_TI | \
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NPCM_DMA_STATUS_TU | \
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NPCM_DMA_STATUS_RI | \
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NPCM_DMA_STATUS_ERI)
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/* Abnormal Interrupt Summary */
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#define NPCM_DMA_STATUS_AIS BIT(15)
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/* Interrupts enabled by AIE */
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#define NPCM_DMA_STATUS_AIS_BITS (NPCM_DMA_STATUS_TPS | \
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NPCM_DMA_STATUS_TJT | \
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NPCM_DMA_STATUS_OVF | \
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NPCM_DMA_STATUS_UNF | \
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NPCM_DMA_STATUS_RU | \
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NPCM_DMA_STATUS_RPS | \
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NPCM_DMA_STATUS_RWT | \
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NPCM_DMA_STATUS_ETI | \
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NPCM_DMA_STATUS_FBI)
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/* Early Receive Interrupt Enable */
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#define NPCM_DMA_INTR_ENAB_ERE BIT(14)
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/* Fatal Bus Error Interrupt Enable */
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#define NPCM_DMA_INTR_ENAB_FBE BIT(13)
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/* Early transmit Interrupt Enable */
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#define NPCM_DMA_INTR_ENAB_ETE BIT(10)
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/* Receive Watchdog Timout Enable */
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#define NPCM_DMA_INTR_ENAB_RWE BIT(9)
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/* Receive Process Stopped Enable */
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#define NPCM_DMA_INTR_ENAB_RSE BIT(8)
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/* Receive Buffer Unavailable Enable */
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#define NPCM_DMA_INTR_ENAB_RUE BIT(7)
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/* Receive Interrupt Enable */
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#define NPCM_DMA_INTR_ENAB_RIE BIT(6)
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/* Transmit Underflow Enable */
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#define NPCM_DMA_INTR_ENAB_UNE BIT(5)
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/* Receive Overflow Enable */
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#define NPCM_DMA_INTR_ENAB_OVE BIT(4)
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/* Transmit Jabber Timeout Enable */
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#define NPCM_DMA_INTR_ENAB_TJE BIT(3)
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/* Transmit Buffer Unavailable Enable */
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#define NPCM_DMA_INTR_ENAB_TUE BIT(2)
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/* Transmit Process Stopped Enable */
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#define NPCM_DMA_INTR_ENAB_TSE BIT(1)
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/* Transmit Interrupt Enable */
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#define NPCM_DMA_INTR_ENAB_TIE BIT(0)
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/* Normal Interrupt Summary Enable */
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#define NPCM_DMA_INTR_ENAB_NIE BIT(16)
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/* Interrupts enabled by NIE Enable */
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#define NPCM_DMA_INTR_ENAB_NIE_BITS (NPCM_DMA_INTR_ENAB_TIE | \
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NPCM_DMA_INTR_ENAB_TUE | \
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NPCM_DMA_INTR_ENAB_RIE | \
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NPCM_DMA_INTR_ENAB_ERE)
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/* Abnormal Interrupt Summary Enable */
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#define NPCM_DMA_INTR_ENAB_AIE BIT(15)
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/* Interrupts enabled by AIE Enable */
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#define NPCM_DMA_INTR_ENAB_AIE_BITS (NPCM_DMA_INTR_ENAB_TSE | \
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NPCM_DMA_INTR_ENAB_TJE | \
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NPCM_DMA_INTR_ENAB_OVE | \
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NPCM_DMA_INTR_ENAB_UNE | \
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NPCM_DMA_INTR_ENAB_RUE | \
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NPCM_DMA_INTR_ENAB_RSE | \
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NPCM_DMA_INTR_ENAB_RWE | \
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NPCM_DMA_INTR_ENAB_ETE | \
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NPCM_DMA_INTR_ENAB_FBE)
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/* Flushing Disabled */
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#define NPCM_DMA_CONTROL_FLUSH_MASK BIT(24)
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/* Start/stop Transmit */
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#define NPCM_DMA_CONTROL_START_STOP_TX BIT(13)
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/* Start/stop Receive */
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#define NPCM_DMA_CONTROL_START_STOP_RX BIT(1)
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/* Next receive descriptor start address */
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#define NPCM_DMA_HOST_RX_DESC_MASK(word) ((uint32_t) (word) & ~3u)
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/* Next transmit descriptor start address */
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#define NPCM_DMA_HOST_TX_DESC_MASK(word) ((uint32_t) (word) & ~3u)
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/* Receive enable */
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#define NPCM_GMAC_MAC_CONFIG_RX_EN BIT(2)
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/* Transmit enable */
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#define NPCM_GMAC_MAC_CONFIG_TX_EN BIT(3)
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/* Frame Receive All */
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#define NPCM_GMAC_FRAME_FILTER_REC_ALL_MASK BIT(31)
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/* Frame HPF Filter*/
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#define NPCM_GMAC_FRAME_FILTER_HPF_MASK BIT(10)
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/* Frame SAF Filter*/
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#define NPCM_GMAC_FRAME_FILTER_SAF_MASK BIT(9)
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/* Frame SAIF Filter*/
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#define NPCM_GMAC_FRAME_FILTER_SAIF_MASK BIT(8)
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/* Frame PCF Filter*/
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#define NPCM_GMAC_FRAME_FILTER_PCF_MASK BIT(word) extract32((word), 6, 2)
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/* Frame DBF Filter*/
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#define NPCM_GMAC_FRAME_FILTER_DBF_MASK BIT(5)
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/* Frame PM Filter*/
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#define NPCM_GMAC_FRAME_FILTER_PM_MASK BIT(4)
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/* Frame DAIF Filter*/
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#define NPCM_GMAC_FRAME_FILTER_DAIF_MASK BIT(3)
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/* Frame HMC Filter*/
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#define NPCM_GMAC_FRAME_FILTER_HMC_MASK BIT(2)
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/* Frame HUC Filter*/
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#define NPCM_GMAC_FRAME_FILTER_HUC_MASK BIT(1)
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/* Frame PR Filter*/
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#define NPCM_GMAC_FRAME_FILTER_PR_MASK BIT(0)
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#endif /* NPCM_GMAC_H */
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