d4c430a80f
QEMU uses a fixed page size for the CPU TLB. If the guest uses large pages then we effectively split these into multiple smaller pages, and populate the corresponding TLB entries on demand. When the guest invalidates the TLB by virtual address we must invalidate all entries covered by the large page. However the address used to invalidate the entry may not be present in the QEMU TLB, so we do not know which regions to clear. Implementing a full vaiable size TLB is hard and slow, so just keep a simple address/mask pair to record which addresses may have been mapped by large pages. If the guest invalidates this region then flush the whole TLB. Signed-off-by: Paul Brook <paul@codesourcery.com> |
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| .. | ||
| cpu.h | ||
| crisv10-decode.h | ||
| crisv32-decode.h | ||
| exec.h | ||
| helper.c | ||
| helper.h | ||
| machine.c | ||
| mmu.c | ||
| mmu.h | ||
| op_helper.c | ||
| opcode-cris.h | ||
| translate_v10.c | ||
| translate.c | ||