a0eaa126af
The problem is that the Linux driver expects the master transaction inhibit bit(R_SPICR_MTI) to be set during driver initialization so that it can detect the fifo size but QEMU defaults it to zero out of reset. The datasheet indicates this bit is active on reset. See page 25, SPI Control Register section: https://www.xilinx.com/content/dam/xilinx/support/documents/ip_documentation/axi_quad_spi/v3_2/pg153-axi-quad-spi.pdf Signed-off-by: Chris Rauer <crauer@google.com> Message-id: 20230323182811.2641044-1-crauer@google.com Reviewed-by: Edgar E. Iglesias <edgar@zeroasic.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org> |
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| .. | ||
| aspeed_smc.c | ||
| ibex_spi_host.c | ||
| imx_spi.c | ||
| Kconfig | ||
| meson.build | ||
| mss-spi.c | ||
| npcm7xx_fiu.c | ||
| npcm_pspi.c | ||
| omap_spi.c | ||
| pl022.c | ||
| sifive_spi.c | ||
| ssi.c | ||
| stm32f2xx_spi.c | ||
| trace-events | ||
| trace.h | ||
| xilinx_spi.c | ||
| xilinx_spips.c | ||
| xlnx-versal-ospi.c | ||