1219 lines
35 KiB
C
1219 lines
35 KiB
C
/*
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* Tiny Code Interpreter for QEMU
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*
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* Copyright (c) 2009, 2011 Stefan Weil
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "config.h"
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/* Defining NDEBUG disables assertions (which makes the code faster). */
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#if !defined(CONFIG_DEBUG_TCG) && !defined(NDEBUG)
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# define NDEBUG
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#endif
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#include "qemu-common.h"
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#include "dyngen-exec.h" /* env */
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#include "exec-all.h" /* MAX_OPC_PARAM_IARGS */
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#include "tcg-op.h"
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/* Marker for missing code. */
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#define TODO() \
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do { \
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fprintf(stderr, "TODO %s:%u: %s()\n", \
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__FILE__, __LINE__, __func__); \
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tcg_abort(); \
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} while (0)
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#if MAX_OPC_PARAM_IARGS != 4
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# error Fix needed, number of supported input arguments changed!
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#endif
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#if TCG_TARGET_REG_BITS == 32
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typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
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tcg_target_ulong, tcg_target_ulong,
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tcg_target_ulong, tcg_target_ulong,
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tcg_target_ulong, tcg_target_ulong);
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#else
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typedef uint64_t (*helper_function)(tcg_target_ulong, tcg_target_ulong,
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tcg_target_ulong, tcg_target_ulong);
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#endif
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/* TCI can optionally use a global register variable for env. */
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#if !defined(AREG0)
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CPUArchState *env;
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#endif
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/* Targets which don't use GETPC also don't need tci_tb_ptr
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which makes them a little faster. */
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#if defined(GETPC)
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uintptr_t tci_tb_ptr;
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#endif
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static tcg_target_ulong tci_reg[TCG_TARGET_NB_REGS];
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#if !defined(CONFIG_TCG_PASS_AREG0)
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# define helper_ldb_mmu(env, addr, mmu_idx) __ldb_mmu(addr, mmu_idx)
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# define helper_ldw_mmu(env, addr, mmu_idx) __ldw_mmu(addr, mmu_idx)
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# define helper_ldl_mmu(env, addr, mmu_idx) __ldl_mmu(addr, mmu_idx)
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# define helper_ldq_mmu(env, addr, mmu_idx) __ldq_mmu(addr, mmu_idx)
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# define helper_stb_mmu(env, addr, val, mmu_idx) __stb_mmu(addr, val, mmu_idx)
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# define helper_stw_mmu(env, addr, val, mmu_idx) __stw_mmu(addr, val, mmu_idx)
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# define helper_stl_mmu(env, addr, val, mmu_idx) __stl_mmu(addr, val, mmu_idx)
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# define helper_stq_mmu(env, addr, val, mmu_idx) __stq_mmu(addr, val, mmu_idx)
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#endif /* !CONFIG_TCG_PASS_AREG0 */
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static tcg_target_ulong tci_read_reg(TCGReg index)
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{
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assert(index < ARRAY_SIZE(tci_reg));
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return tci_reg[index];
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}
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#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
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static int8_t tci_read_reg8s(TCGReg index)
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{
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return (int8_t)tci_read_reg(index);
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}
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#endif
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#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
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static int16_t tci_read_reg16s(TCGReg index)
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{
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return (int16_t)tci_read_reg(index);
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}
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#endif
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#if TCG_TARGET_REG_BITS == 64
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static int32_t tci_read_reg32s(TCGReg index)
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{
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return (int32_t)tci_read_reg(index);
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}
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#endif
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static uint8_t tci_read_reg8(TCGReg index)
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{
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return (uint8_t)tci_read_reg(index);
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}
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static uint16_t tci_read_reg16(TCGReg index)
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{
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return (uint16_t)tci_read_reg(index);
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}
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static uint32_t tci_read_reg32(TCGReg index)
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{
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return (uint32_t)tci_read_reg(index);
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}
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#if TCG_TARGET_REG_BITS == 64
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static uint64_t tci_read_reg64(TCGReg index)
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{
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return tci_read_reg(index);
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}
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#endif
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static void tci_write_reg(TCGReg index, tcg_target_ulong value)
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{
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assert(index < ARRAY_SIZE(tci_reg));
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assert(index != TCG_AREG0);
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tci_reg[index] = value;
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}
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static void tci_write_reg8s(TCGReg index, int8_t value)
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{
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tci_write_reg(index, value);
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}
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static void tci_write_reg16s(TCGReg index, int16_t value)
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{
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tci_write_reg(index, value);
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}
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#if TCG_TARGET_REG_BITS == 64
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static void tci_write_reg32s(TCGReg index, int32_t value)
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{
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tci_write_reg(index, value);
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}
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#endif
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static void tci_write_reg8(TCGReg index, uint8_t value)
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{
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tci_write_reg(index, value);
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}
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static void tci_write_reg16(TCGReg index, uint16_t value)
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{
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tci_write_reg(index, value);
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}
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static void tci_write_reg32(TCGReg index, uint32_t value)
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{
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tci_write_reg(index, value);
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}
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#if TCG_TARGET_REG_BITS == 32
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static void tci_write_reg64(uint32_t high_index, uint32_t low_index,
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uint64_t value)
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{
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tci_write_reg(low_index, value);
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tci_write_reg(high_index, value >> 32);
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}
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#elif TCG_TARGET_REG_BITS == 64
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static void tci_write_reg64(TCGReg index, uint64_t value)
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{
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tci_write_reg(index, value);
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}
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#endif
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#if TCG_TARGET_REG_BITS == 32
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/* Create a 64 bit value from two 32 bit values. */
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static uint64_t tci_uint64(uint32_t high, uint32_t low)
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{
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return ((uint64_t)high << 32) + low;
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}
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#endif
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/* Read constant (native size) from bytecode. */
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static tcg_target_ulong tci_read_i(uint8_t **tb_ptr)
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{
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tcg_target_ulong value = *(tcg_target_ulong *)(*tb_ptr);
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*tb_ptr += sizeof(value);
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return value;
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}
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/* Read constant (32 bit) from bytecode. */
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static uint32_t tci_read_i32(uint8_t **tb_ptr)
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{
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uint32_t value = *(uint32_t *)(*tb_ptr);
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*tb_ptr += sizeof(value);
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return value;
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}
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#if TCG_TARGET_REG_BITS == 64
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/* Read constant (64 bit) from bytecode. */
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static uint64_t tci_read_i64(uint8_t **tb_ptr)
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{
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uint64_t value = *(uint64_t *)(*tb_ptr);
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*tb_ptr += sizeof(value);
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return value;
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}
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#endif
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/* Read indexed register (native size) from bytecode. */
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static tcg_target_ulong tci_read_r(uint8_t **tb_ptr)
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{
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tcg_target_ulong value = tci_read_reg(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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/* Read indexed register (8 bit) from bytecode. */
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static uint8_t tci_read_r8(uint8_t **tb_ptr)
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{
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uint8_t value = tci_read_reg8(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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#if TCG_TARGET_HAS_ext8s_i32 || TCG_TARGET_HAS_ext8s_i64
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/* Read indexed register (8 bit signed) from bytecode. */
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static int8_t tci_read_r8s(uint8_t **tb_ptr)
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{
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int8_t value = tci_read_reg8s(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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#endif
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/* Read indexed register (16 bit) from bytecode. */
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static uint16_t tci_read_r16(uint8_t **tb_ptr)
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{
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uint16_t value = tci_read_reg16(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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#if TCG_TARGET_HAS_ext16s_i32 || TCG_TARGET_HAS_ext16s_i64
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/* Read indexed register (16 bit signed) from bytecode. */
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static int16_t tci_read_r16s(uint8_t **tb_ptr)
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{
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int16_t value = tci_read_reg16s(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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#endif
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/* Read indexed register (32 bit) from bytecode. */
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static uint32_t tci_read_r32(uint8_t **tb_ptr)
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{
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uint32_t value = tci_read_reg32(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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#if TCG_TARGET_REG_BITS == 32
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/* Read two indexed registers (2 * 32 bit) from bytecode. */
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static uint64_t tci_read_r64(uint8_t **tb_ptr)
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{
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uint32_t low = tci_read_r32(tb_ptr);
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return tci_uint64(tci_read_r32(tb_ptr), low);
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}
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#elif TCG_TARGET_REG_BITS == 64
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/* Read indexed register (32 bit signed) from bytecode. */
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static int32_t tci_read_r32s(uint8_t **tb_ptr)
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{
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int32_t value = tci_read_reg32s(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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/* Read indexed register (64 bit) from bytecode. */
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static uint64_t tci_read_r64(uint8_t **tb_ptr)
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{
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uint64_t value = tci_read_reg64(**tb_ptr);
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*tb_ptr += 1;
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return value;
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}
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#endif
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/* Read indexed register(s) with target address from bytecode. */
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static target_ulong tci_read_ulong(uint8_t **tb_ptr)
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{
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target_ulong taddr = tci_read_r(tb_ptr);
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#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
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taddr += (uint64_t)tci_read_r(tb_ptr) << 32;
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#endif
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return taddr;
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}
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/* Read indexed register or constant (native size) from bytecode. */
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static tcg_target_ulong tci_read_ri(uint8_t **tb_ptr)
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{
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tcg_target_ulong value;
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TCGReg r = **tb_ptr;
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*tb_ptr += 1;
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if (r == TCG_CONST) {
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value = tci_read_i(tb_ptr);
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} else {
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value = tci_read_reg(r);
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}
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return value;
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}
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/* Read indexed register or constant (32 bit) from bytecode. */
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static uint32_t tci_read_ri32(uint8_t **tb_ptr)
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{
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uint32_t value;
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TCGReg r = **tb_ptr;
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*tb_ptr += 1;
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if (r == TCG_CONST) {
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value = tci_read_i32(tb_ptr);
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} else {
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value = tci_read_reg32(r);
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}
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return value;
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}
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#if TCG_TARGET_REG_BITS == 32
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/* Read two indexed registers or constants (2 * 32 bit) from bytecode. */
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static uint64_t tci_read_ri64(uint8_t **tb_ptr)
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{
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uint32_t low = tci_read_ri32(tb_ptr);
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return tci_uint64(tci_read_ri32(tb_ptr), low);
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}
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#elif TCG_TARGET_REG_BITS == 64
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/* Read indexed register or constant (64 bit) from bytecode. */
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static uint64_t tci_read_ri64(uint8_t **tb_ptr)
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{
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uint64_t value;
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TCGReg r = **tb_ptr;
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*tb_ptr += 1;
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if (r == TCG_CONST) {
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value = tci_read_i64(tb_ptr);
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} else {
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value = tci_read_reg64(r);
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}
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return value;
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}
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#endif
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static target_ulong tci_read_label(uint8_t **tb_ptr)
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{
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target_ulong label = tci_read_i(tb_ptr);
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assert(label != 0);
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return label;
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}
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static bool tci_compare32(uint32_t u0, uint32_t u1, TCGCond condition)
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{
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bool result = false;
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int32_t i0 = u0;
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int32_t i1 = u1;
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switch (condition) {
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case TCG_COND_EQ:
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result = (u0 == u1);
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break;
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case TCG_COND_NE:
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result = (u0 != u1);
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break;
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case TCG_COND_LT:
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result = (i0 < i1);
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break;
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case TCG_COND_GE:
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result = (i0 >= i1);
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break;
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case TCG_COND_LE:
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result = (i0 <= i1);
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break;
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case TCG_COND_GT:
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result = (i0 > i1);
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break;
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case TCG_COND_LTU:
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result = (u0 < u1);
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break;
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case TCG_COND_GEU:
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result = (u0 >= u1);
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break;
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case TCG_COND_LEU:
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result = (u0 <= u1);
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break;
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case TCG_COND_GTU:
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result = (u0 > u1);
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break;
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default:
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TODO();
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}
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return result;
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}
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static bool tci_compare64(uint64_t u0, uint64_t u1, TCGCond condition)
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{
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bool result = false;
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int64_t i0 = u0;
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int64_t i1 = u1;
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switch (condition) {
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case TCG_COND_EQ:
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result = (u0 == u1);
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break;
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case TCG_COND_NE:
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result = (u0 != u1);
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break;
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case TCG_COND_LT:
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result = (i0 < i1);
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break;
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case TCG_COND_GE:
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result = (i0 >= i1);
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break;
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case TCG_COND_LE:
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result = (i0 <= i1);
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break;
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case TCG_COND_GT:
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result = (i0 > i1);
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break;
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case TCG_COND_LTU:
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result = (u0 < u1);
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break;
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case TCG_COND_GEU:
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result = (u0 >= u1);
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break;
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case TCG_COND_LEU:
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result = (u0 <= u1);
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break;
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case TCG_COND_GTU:
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result = (u0 > u1);
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break;
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default:
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TODO();
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}
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return result;
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}
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/* Interpret pseudo code in tb. */
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tcg_target_ulong tcg_qemu_tb_exec(CPUArchState *cpustate, uint8_t *tb_ptr)
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{
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tcg_target_ulong next_tb = 0;
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env = cpustate;
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tci_reg[TCG_AREG0] = (tcg_target_ulong)env;
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assert(tb_ptr);
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for (;;) {
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#if defined(GETPC)
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tci_tb_ptr = (uintptr_t)tb_ptr;
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#endif
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TCGOpcode opc = tb_ptr[0];
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#if !defined(NDEBUG)
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uint8_t op_size = tb_ptr[1];
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uint8_t *old_code_ptr = tb_ptr;
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#endif
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tcg_target_ulong t0;
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tcg_target_ulong t1;
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tcg_target_ulong t2;
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tcg_target_ulong label;
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TCGCond condition;
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target_ulong taddr;
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#ifndef CONFIG_SOFTMMU
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tcg_target_ulong host_addr;
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#endif
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uint8_t tmp8;
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uint16_t tmp16;
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uint32_t tmp32;
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uint64_t tmp64;
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#if TCG_TARGET_REG_BITS == 32
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uint64_t v64;
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#endif
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/* Skip opcode and size entry. */
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tb_ptr += 2;
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switch (opc) {
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case INDEX_op_end:
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case INDEX_op_nop:
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break;
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case INDEX_op_nop1:
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case INDEX_op_nop2:
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case INDEX_op_nop3:
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case INDEX_op_nopn:
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case INDEX_op_discard:
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TODO();
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break;
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case INDEX_op_set_label:
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TODO();
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break;
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case INDEX_op_call:
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t0 = tci_read_ri(&tb_ptr);
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#if TCG_TARGET_REG_BITS == 32
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tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
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tci_read_reg(TCG_REG_R1),
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|
tci_read_reg(TCG_REG_R2),
|
|
tci_read_reg(TCG_REG_R3),
|
|
tci_read_reg(TCG_REG_R5),
|
|
tci_read_reg(TCG_REG_R6),
|
|
tci_read_reg(TCG_REG_R7),
|
|
tci_read_reg(TCG_REG_R8));
|
|
tci_write_reg(TCG_REG_R0, tmp64);
|
|
tci_write_reg(TCG_REG_R1, tmp64 >> 32);
|
|
#else
|
|
tmp64 = ((helper_function)t0)(tci_read_reg(TCG_REG_R0),
|
|
tci_read_reg(TCG_REG_R1),
|
|
tci_read_reg(TCG_REG_R2),
|
|
tci_read_reg(TCG_REG_R3));
|
|
tci_write_reg(TCG_REG_R0, tmp64);
|
|
#endif
|
|
break;
|
|
case INDEX_op_jmp:
|
|
case INDEX_op_br:
|
|
label = tci_read_label(&tb_ptr);
|
|
assert(tb_ptr == old_code_ptr + op_size);
|
|
tb_ptr = (uint8_t *)label;
|
|
continue;
|
|
case INDEX_op_setcond_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
condition = *tb_ptr++;
|
|
tci_write_reg32(t0, tci_compare32(t1, t2, condition));
|
|
break;
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
case INDEX_op_setcond2_i32:
|
|
t0 = *tb_ptr++;
|
|
tmp64 = tci_read_r64(&tb_ptr);
|
|
v64 = tci_read_ri64(&tb_ptr);
|
|
condition = *tb_ptr++;
|
|
tci_write_reg32(t0, tci_compare64(tmp64, v64, condition));
|
|
break;
|
|
#elif TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_setcond_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
condition = *tb_ptr++;
|
|
tci_write_reg64(t0, tci_compare64(t1, t2, condition));
|
|
break;
|
|
#endif
|
|
case INDEX_op_mov_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32(&tb_ptr);
|
|
tci_write_reg32(t0, t1);
|
|
break;
|
|
case INDEX_op_movi_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_i32(&tb_ptr);
|
|
tci_write_reg32(t0, t1);
|
|
break;
|
|
|
|
/* Load/store operations (32 bit). */
|
|
|
|
case INDEX_op_ld8u_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
|
|
break;
|
|
case INDEX_op_ld8s_i32:
|
|
case INDEX_op_ld16u_i32:
|
|
TODO();
|
|
break;
|
|
case INDEX_op_ld16s_i32:
|
|
TODO();
|
|
break;
|
|
case INDEX_op_ld_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
|
|
break;
|
|
case INDEX_op_st8_i32:
|
|
t0 = tci_read_r8(&tb_ptr);
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
*(uint8_t *)(t1 + t2) = t0;
|
|
break;
|
|
case INDEX_op_st16_i32:
|
|
t0 = tci_read_r16(&tb_ptr);
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
*(uint16_t *)(t1 + t2) = t0;
|
|
break;
|
|
case INDEX_op_st_i32:
|
|
t0 = tci_read_r32(&tb_ptr);
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
*(uint32_t *)(t1 + t2) = t0;
|
|
break;
|
|
|
|
/* Arithmetic operations (32 bit). */
|
|
|
|
case INDEX_op_add_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 + t2);
|
|
break;
|
|
case INDEX_op_sub_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 - t2);
|
|
break;
|
|
case INDEX_op_mul_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 * t2);
|
|
break;
|
|
#if TCG_TARGET_HAS_div_i32
|
|
case INDEX_op_div_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, (int32_t)t1 / (int32_t)t2);
|
|
break;
|
|
case INDEX_op_divu_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 / t2);
|
|
break;
|
|
case INDEX_op_rem_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, (int32_t)t1 % (int32_t)t2);
|
|
break;
|
|
case INDEX_op_remu_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 % t2);
|
|
break;
|
|
#elif TCG_TARGET_HAS_div2_i32
|
|
case INDEX_op_div2_i32:
|
|
case INDEX_op_divu2_i32:
|
|
TODO();
|
|
break;
|
|
#endif
|
|
case INDEX_op_and_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 & t2);
|
|
break;
|
|
case INDEX_op_or_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 | t2);
|
|
break;
|
|
case INDEX_op_xor_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 ^ t2);
|
|
break;
|
|
|
|
/* Shift/rotate operations (32 bit). */
|
|
|
|
case INDEX_op_shl_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 << t2);
|
|
break;
|
|
case INDEX_op_shr_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, t1 >> t2);
|
|
break;
|
|
case INDEX_op_sar_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, ((int32_t)t1 >> t2));
|
|
break;
|
|
#if TCG_TARGET_HAS_rot_i32
|
|
case INDEX_op_rotl_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, (t1 << t2) | (t1 >> (32 - t2)));
|
|
break;
|
|
case INDEX_op_rotr_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
t2 = tci_read_ri32(&tb_ptr);
|
|
tci_write_reg32(t0, (t1 >> t2) | (t1 << (32 - t2)));
|
|
break;
|
|
#endif
|
|
case INDEX_op_brcond_i32:
|
|
t0 = tci_read_r32(&tb_ptr);
|
|
t1 = tci_read_ri32(&tb_ptr);
|
|
condition = *tb_ptr++;
|
|
label = tci_read_label(&tb_ptr);
|
|
if (tci_compare32(t0, t1, condition)) {
|
|
assert(tb_ptr == old_code_ptr + op_size);
|
|
tb_ptr = (uint8_t *)label;
|
|
continue;
|
|
}
|
|
break;
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
case INDEX_op_add2_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = *tb_ptr++;
|
|
tmp64 = tci_read_r64(&tb_ptr);
|
|
tmp64 += tci_read_r64(&tb_ptr);
|
|
tci_write_reg64(t1, t0, tmp64);
|
|
break;
|
|
case INDEX_op_sub2_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = *tb_ptr++;
|
|
tmp64 = tci_read_r64(&tb_ptr);
|
|
tmp64 -= tci_read_r64(&tb_ptr);
|
|
tci_write_reg64(t1, t0, tmp64);
|
|
break;
|
|
case INDEX_op_brcond2_i32:
|
|
tmp64 = tci_read_r64(&tb_ptr);
|
|
v64 = tci_read_ri64(&tb_ptr);
|
|
condition = *tb_ptr++;
|
|
label = tci_read_label(&tb_ptr);
|
|
if (tci_compare64(tmp64, v64, condition)) {
|
|
assert(tb_ptr == old_code_ptr + op_size);
|
|
tb_ptr = (uint8_t *)label;
|
|
continue;
|
|
}
|
|
break;
|
|
case INDEX_op_mulu2_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = *tb_ptr++;
|
|
t2 = tci_read_r32(&tb_ptr);
|
|
tmp64 = tci_read_r32(&tb_ptr);
|
|
tci_write_reg64(t1, t0, t2 * tmp64);
|
|
break;
|
|
#endif /* TCG_TARGET_REG_BITS == 32 */
|
|
#if TCG_TARGET_HAS_ext8s_i32
|
|
case INDEX_op_ext8s_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r8s(&tb_ptr);
|
|
tci_write_reg32(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext16s_i32
|
|
case INDEX_op_ext16s_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r16s(&tb_ptr);
|
|
tci_write_reg32(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext8u_i32
|
|
case INDEX_op_ext8u_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r8(&tb_ptr);
|
|
tci_write_reg32(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext16u_i32
|
|
case INDEX_op_ext16u_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r16(&tb_ptr);
|
|
tci_write_reg32(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_bswap16_i32
|
|
case INDEX_op_bswap16_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r16(&tb_ptr);
|
|
tci_write_reg32(t0, bswap16(t1));
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_bswap32_i32
|
|
case INDEX_op_bswap32_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32(&tb_ptr);
|
|
tci_write_reg32(t0, bswap32(t1));
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_not_i32
|
|
case INDEX_op_not_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32(&tb_ptr);
|
|
tci_write_reg32(t0, ~t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_neg_i32
|
|
case INDEX_op_neg_i32:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32(&tb_ptr);
|
|
tci_write_reg32(t0, -t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_mov_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r64(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
case INDEX_op_movi_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_i64(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
|
|
/* Load/store operations (64 bit). */
|
|
|
|
case INDEX_op_ld8u_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
tci_write_reg8(t0, *(uint8_t *)(t1 + t2));
|
|
break;
|
|
case INDEX_op_ld8s_i64:
|
|
case INDEX_op_ld16u_i64:
|
|
case INDEX_op_ld16s_i64:
|
|
TODO();
|
|
break;
|
|
case INDEX_op_ld32u_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
tci_write_reg32(t0, *(uint32_t *)(t1 + t2));
|
|
break;
|
|
case INDEX_op_ld32s_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
tci_write_reg32s(t0, *(int32_t *)(t1 + t2));
|
|
break;
|
|
case INDEX_op_ld_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
tci_write_reg64(t0, *(uint64_t *)(t1 + t2));
|
|
break;
|
|
case INDEX_op_st8_i64:
|
|
t0 = tci_read_r8(&tb_ptr);
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
*(uint8_t *)(t1 + t2) = t0;
|
|
break;
|
|
case INDEX_op_st16_i64:
|
|
t0 = tci_read_r16(&tb_ptr);
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
*(uint16_t *)(t1 + t2) = t0;
|
|
break;
|
|
case INDEX_op_st32_i64:
|
|
t0 = tci_read_r32(&tb_ptr);
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
*(uint32_t *)(t1 + t2) = t0;
|
|
break;
|
|
case INDEX_op_st_i64:
|
|
t0 = tci_read_r64(&tb_ptr);
|
|
t1 = tci_read_r(&tb_ptr);
|
|
t2 = tci_read_i32(&tb_ptr);
|
|
*(uint64_t *)(t1 + t2) = t0;
|
|
break;
|
|
|
|
/* Arithmetic operations (64 bit). */
|
|
|
|
case INDEX_op_add_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 + t2);
|
|
break;
|
|
case INDEX_op_sub_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 - t2);
|
|
break;
|
|
case INDEX_op_mul_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 * t2);
|
|
break;
|
|
#if TCG_TARGET_HAS_div_i64
|
|
case INDEX_op_div_i64:
|
|
case INDEX_op_divu_i64:
|
|
case INDEX_op_rem_i64:
|
|
case INDEX_op_remu_i64:
|
|
TODO();
|
|
break;
|
|
#elif TCG_TARGET_HAS_div2_i64
|
|
case INDEX_op_div2_i64:
|
|
case INDEX_op_divu2_i64:
|
|
TODO();
|
|
break;
|
|
#endif
|
|
case INDEX_op_and_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 & t2);
|
|
break;
|
|
case INDEX_op_or_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 | t2);
|
|
break;
|
|
case INDEX_op_xor_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 ^ t2);
|
|
break;
|
|
|
|
/* Shift/rotate operations (64 bit). */
|
|
|
|
case INDEX_op_shl_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 << t2);
|
|
break;
|
|
case INDEX_op_shr_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, t1 >> t2);
|
|
break;
|
|
case INDEX_op_sar_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
t2 = tci_read_ri64(&tb_ptr);
|
|
tci_write_reg64(t0, ((int64_t)t1 >> t2));
|
|
break;
|
|
#if TCG_TARGET_HAS_rot_i64
|
|
case INDEX_op_rotl_i64:
|
|
case INDEX_op_rotr_i64:
|
|
TODO();
|
|
break;
|
|
#endif
|
|
case INDEX_op_brcond_i64:
|
|
t0 = tci_read_r64(&tb_ptr);
|
|
t1 = tci_read_ri64(&tb_ptr);
|
|
condition = *tb_ptr++;
|
|
label = tci_read_label(&tb_ptr);
|
|
if (tci_compare64(t0, t1, condition)) {
|
|
assert(tb_ptr == old_code_ptr + op_size);
|
|
tb_ptr = (uint8_t *)label;
|
|
continue;
|
|
}
|
|
break;
|
|
#if TCG_TARGET_HAS_ext8u_i64
|
|
case INDEX_op_ext8u_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r8(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext8s_i64
|
|
case INDEX_op_ext8s_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r8s(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext16s_i64
|
|
case INDEX_op_ext16s_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r16s(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext16u_i64
|
|
case INDEX_op_ext16u_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r16(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext32s_i64
|
|
case INDEX_op_ext32s_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32s(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_ext32u_i64
|
|
case INDEX_op_ext32u_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32(&tb_ptr);
|
|
tci_write_reg64(t0, t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_bswap16_i64
|
|
case INDEX_op_bswap16_i64:
|
|
TODO();
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r16(&tb_ptr);
|
|
tci_write_reg64(t0, bswap16(t1));
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_bswap32_i64
|
|
case INDEX_op_bswap32_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r32(&tb_ptr);
|
|
tci_write_reg64(t0, bswap32(t1));
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_bswap64_i64
|
|
case INDEX_op_bswap64_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r64(&tb_ptr);
|
|
tci_write_reg64(t0, bswap64(t1));
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_not_i64
|
|
case INDEX_op_not_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r64(&tb_ptr);
|
|
tci_write_reg64(t0, ~t1);
|
|
break;
|
|
#endif
|
|
#if TCG_TARGET_HAS_neg_i64
|
|
case INDEX_op_neg_i64:
|
|
t0 = *tb_ptr++;
|
|
t1 = tci_read_r64(&tb_ptr);
|
|
tci_write_reg64(t0, -t1);
|
|
break;
|
|
#endif
|
|
#endif /* TCG_TARGET_REG_BITS == 64 */
|
|
|
|
/* QEMU specific operations. */
|
|
|
|
#if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
|
|
case INDEX_op_debug_insn_start:
|
|
TODO();
|
|
break;
|
|
#else
|
|
case INDEX_op_debug_insn_start:
|
|
TODO();
|
|
break;
|
|
#endif
|
|
case INDEX_op_exit_tb:
|
|
next_tb = *(uint64_t *)tb_ptr;
|
|
goto exit;
|
|
break;
|
|
case INDEX_op_goto_tb:
|
|
t0 = tci_read_i32(&tb_ptr);
|
|
assert(tb_ptr == old_code_ptr + op_size);
|
|
tb_ptr += (int32_t)t0;
|
|
continue;
|
|
case INDEX_op_qemu_ld8u:
|
|
t0 = *tb_ptr++;
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
|
|
#endif
|
|
tci_write_reg8(t0, tmp8);
|
|
break;
|
|
case INDEX_op_qemu_ld8s:
|
|
t0 = *tb_ptr++;
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp8 = helper_ldb_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp8 = *(uint8_t *)(host_addr + GUEST_BASE);
|
|
#endif
|
|
tci_write_reg8s(t0, tmp8);
|
|
break;
|
|
case INDEX_op_qemu_ld16u:
|
|
t0 = *tb_ptr++;
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
|
|
#endif
|
|
tci_write_reg16(t0, tmp16);
|
|
break;
|
|
case INDEX_op_qemu_ld16s:
|
|
t0 = *tb_ptr++;
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp16 = helper_ldw_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp16 = tswap16(*(uint16_t *)(host_addr + GUEST_BASE));
|
|
#endif
|
|
tci_write_reg16s(t0, tmp16);
|
|
break;
|
|
#if TCG_TARGET_REG_BITS == 64
|
|
case INDEX_op_qemu_ld32u:
|
|
t0 = *tb_ptr++;
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
|
|
#endif
|
|
tci_write_reg32(t0, tmp32);
|
|
break;
|
|
case INDEX_op_qemu_ld32s:
|
|
t0 = *tb_ptr++;
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
|
|
#endif
|
|
tci_write_reg32s(t0, tmp32);
|
|
break;
|
|
#endif /* TCG_TARGET_REG_BITS == 64 */
|
|
case INDEX_op_qemu_ld32:
|
|
t0 = *tb_ptr++;
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp32 = helper_ldl_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp32 = tswap32(*(uint32_t *)(host_addr + GUEST_BASE));
|
|
#endif
|
|
tci_write_reg32(t0, tmp32);
|
|
break;
|
|
case INDEX_op_qemu_ld64:
|
|
t0 = *tb_ptr++;
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
t1 = *tb_ptr++;
|
|
#endif
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
tmp64 = helper_ldq_mmu(env, taddr, tci_read_i(&tb_ptr));
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
tmp64 = tswap64(*(uint64_t *)(host_addr + GUEST_BASE));
|
|
#endif
|
|
tci_write_reg(t0, tmp64);
|
|
#if TCG_TARGET_REG_BITS == 32
|
|
tci_write_reg(t1, tmp64 >> 32);
|
|
#endif
|
|
break;
|
|
case INDEX_op_qemu_st8:
|
|
t0 = tci_read_r8(&tb_ptr);
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
t2 = tci_read_i(&tb_ptr);
|
|
helper_stb_mmu(env, taddr, t0, t2);
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
*(uint8_t *)(host_addr + GUEST_BASE) = t0;
|
|
#endif
|
|
break;
|
|
case INDEX_op_qemu_st16:
|
|
t0 = tci_read_r16(&tb_ptr);
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
t2 = tci_read_i(&tb_ptr);
|
|
helper_stw_mmu(env, taddr, t0, t2);
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
*(uint16_t *)(host_addr + GUEST_BASE) = tswap16(t0);
|
|
#endif
|
|
break;
|
|
case INDEX_op_qemu_st32:
|
|
t0 = tci_read_r32(&tb_ptr);
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
t2 = tci_read_i(&tb_ptr);
|
|
helper_stl_mmu(env, taddr, t0, t2);
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
*(uint32_t *)(host_addr + GUEST_BASE) = tswap32(t0);
|
|
#endif
|
|
break;
|
|
case INDEX_op_qemu_st64:
|
|
tmp64 = tci_read_r64(&tb_ptr);
|
|
taddr = tci_read_ulong(&tb_ptr);
|
|
#ifdef CONFIG_SOFTMMU
|
|
t2 = tci_read_i(&tb_ptr);
|
|
helper_stq_mmu(env, taddr, tmp64, t2);
|
|
#else
|
|
host_addr = (tcg_target_ulong)taddr;
|
|
assert(taddr == host_addr);
|
|
*(uint64_t *)(host_addr + GUEST_BASE) = tswap64(tmp64);
|
|
#endif
|
|
break;
|
|
default:
|
|
TODO();
|
|
break;
|
|
}
|
|
assert(tb_ptr == old_code_ptr + op_size);
|
|
}
|
|
exit:
|
|
return next_tb;
|
|
}
|