James Hogan b74cddcbf6 target/mips: Use BS_EXCP where interrupts are expected ... Commit e350d8ca3a ("target/mips: optimize indirect branches") made indirect branches able to directly find the next TB and jump straight to it without breaking out of translated code and going around the main execution loop. This breaks the assumption in target/mips/translate.c that BS_STOP is sufficient to cause pending interrupts to be handled, since interrupts are only checked in the main loop. Fix a few of these assumptions by using gen_save_pc to update the saved PC and using BS_EXCP instead of BS_STOP: - [D]MFC0 CP0_Count may trigger a timer interrupt which should be immediately handled. - [D]MTC0 CP0_Cause may trigger an interrupt (but in fact translation was only even being stopped in the DMTC0 case). - [D]MTC0 CP0_<any> when icount is used is assumed could potentially cause interrupts. - EI may trigger an interrupt which was pending. I specifically hit this case when running KVM nested in mipsel-softmmu. A timer interrupt while the 2nd guest was executing is caught by KVM which switches back to the normal Linux exception base and re-enables interrupts with EI. Since the above commit QEMU doesn't leave translated code until the nested KVM has already restored the KVM exception base and returned to the 2nd guest, at which point it is too late to check for pending interrupts and it gets stuck in an infinite loop of unhandled interrupts. Something similar was needed for ARM in commit b29fd33db5 ("target/arm: use DISAS_EXIT for eret handling"). Fixes: e350d8ca3a ("target/mips: optimize indirect branches") Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Yongbok Kim <yongbok.kim@imgtec.com> Cc: Richard Henderson <rth@twiddle.net> Reviewed-by: Richard Henderson <rth@twiddle.net> Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>		2017-08-02 22:18:12 +01:00
..
cpu-qom.h
cpu.c	qom/cpu: move tlb_flush to cpu_common_reset	2017-01-13 14:24:31 +00:00
cpu.h	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
dsp_helper.c
gdbstub.c
helper.c	mips: Add KVM T&E segment support for TCG	2017-08-02 22:18:06 +01:00
helper.h	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
kvm_mips.h
kvm.c	vcpu_dirty: share the same field in CPUState for all accelerators	2017-07-04 14:30:03 +02:00
lmi_helper.c
machine.c	target/mips: Add segmentation control registers	2017-07-20 22:42:26 +01:00
Makefile.objs
mips-defs.h
mips-semi.c
msa_helper.c
op_helper.c	target-mips: apply CP0.PageMask before writing into TLB entry	2017-08-02 22:18:11 +01:00
TODO
trace-events	docs: fix broken paths to docs/devel/tracing.txt	2017-07-31 13:12:53 +03:00
translate_init.c	target/mips: Enable CP0_EBase.WG on MIPS64 CPUs	2017-07-21 03:23:44 +01:00
translate.c	target/mips: Use BS_EXCP where interrupts are expected	2017-08-02 22:18:12 +01:00