a953b5fa15
Now that CPUNegativeOffsetState is part of CPUState, we can reference it directly. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
235 lines
6.6 KiB
C
235 lines
6.6 KiB
C
/*
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* QEMU TCG vCPU common functionality
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*
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* Functionality common to all TCG vCPU variants: mttcg, rr and icount.
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*
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* Copyright (c) 2003-2008 Fabrice Bellard
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* Copyright (c) 2014 Red Hat Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "sysemu/tcg.h"
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#include "sysemu/replay.h"
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#include "sysemu/cpu-timers.h"
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#include "qemu/main-loop.h"
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#include "qemu/guest-random.h"
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#include "qemu/timer.h"
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#include "exec/exec-all.h"
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#include "exec/hwaddr.h"
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#include "exec/gdbstub.h"
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#include "tcg-accel-ops.h"
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#include "tcg-accel-ops-mttcg.h"
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#include "tcg-accel-ops-rr.h"
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#include "tcg-accel-ops-icount.h"
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/* common functionality among all TCG variants */
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void tcg_cpu_init_cflags(CPUState *cpu, bool parallel)
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{
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uint32_t cflags;
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/*
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* Include the cluster number in the hash we use to look up TBs.
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* This is important because a TB that is valid for one cluster at
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* a given physical address and set of CPU flags is not necessarily
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* valid for another:
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* the two clusters may have different views of physical memory, or
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* may have different CPU features (eg FPU present or absent).
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*/
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cflags = cpu->cluster_index << CF_CLUSTER_SHIFT;
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cflags |= parallel ? CF_PARALLEL : 0;
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cflags |= icount_enabled() ? CF_USE_ICOUNT : 0;
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cpu->tcg_cflags |= cflags;
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}
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void tcg_cpus_destroy(CPUState *cpu)
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{
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cpu_thread_signal_destroyed(cpu);
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}
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int tcg_cpus_exec(CPUState *cpu)
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{
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int ret;
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assert(tcg_enabled());
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cpu_exec_start(cpu);
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ret = cpu_exec(cpu);
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cpu_exec_end(cpu);
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return ret;
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}
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/* mask must never be zero, except for A20 change call */
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void tcg_handle_interrupt(CPUState *cpu, int mask)
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{
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g_assert(qemu_mutex_iothread_locked());
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cpu->interrupt_request |= mask;
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/*
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* If called from iothread context, wake the target cpu in
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* case its halted.
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*/
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if (!qemu_cpu_is_self(cpu)) {
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qemu_cpu_kick(cpu);
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} else {
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qatomic_set(&cpu->neg.icount_decr.u16.high, -1);
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}
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}
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static bool tcg_supports_guest_debug(void)
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{
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return true;
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}
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/* Translate GDB watchpoint type to a flags value for cpu_watchpoint_* */
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static inline int xlat_gdb_type(CPUState *cpu, int gdbtype)
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{
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static const int xlat[] = {
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[GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
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[GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
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[GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
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};
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CPUClass *cc = CPU_GET_CLASS(cpu);
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int cputype = xlat[gdbtype];
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if (cc->gdb_stop_before_watchpoint) {
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cputype |= BP_STOP_BEFORE_ACCESS;
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}
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return cputype;
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}
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static int tcg_insert_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
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{
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CPUState *cpu;
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int err = 0;
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switch (type) {
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case GDB_BREAKPOINT_SW:
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case GDB_BREAKPOINT_HW:
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CPU_FOREACH(cpu) {
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err = cpu_breakpoint_insert(cpu, addr, BP_GDB, NULL);
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if (err) {
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break;
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}
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}
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return err;
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case GDB_WATCHPOINT_WRITE:
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case GDB_WATCHPOINT_READ:
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case GDB_WATCHPOINT_ACCESS:
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CPU_FOREACH(cpu) {
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err = cpu_watchpoint_insert(cpu, addr, len,
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xlat_gdb_type(cpu, type), NULL);
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if (err) {
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break;
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}
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}
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return err;
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default:
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return -ENOSYS;
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}
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}
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static int tcg_remove_breakpoint(CPUState *cs, int type, vaddr addr, vaddr len)
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{
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CPUState *cpu;
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int err = 0;
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switch (type) {
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case GDB_BREAKPOINT_SW:
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case GDB_BREAKPOINT_HW:
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CPU_FOREACH(cpu) {
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err = cpu_breakpoint_remove(cpu, addr, BP_GDB);
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if (err) {
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break;
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}
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}
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return err;
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case GDB_WATCHPOINT_WRITE:
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case GDB_WATCHPOINT_READ:
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case GDB_WATCHPOINT_ACCESS:
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CPU_FOREACH(cpu) {
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err = cpu_watchpoint_remove(cpu, addr, len,
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xlat_gdb_type(cpu, type));
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if (err) {
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break;
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}
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}
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return err;
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default:
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return -ENOSYS;
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}
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}
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static inline void tcg_remove_all_breakpoints(CPUState *cpu)
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{
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cpu_breakpoint_remove_all(cpu, BP_GDB);
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cpu_watchpoint_remove_all(cpu, BP_GDB);
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}
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static void tcg_accel_ops_init(AccelOpsClass *ops)
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{
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if (qemu_tcg_mttcg_enabled()) {
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ops->create_vcpu_thread = mttcg_start_vcpu_thread;
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ops->kick_vcpu_thread = mttcg_kick_vcpu_thread;
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ops->handle_interrupt = tcg_handle_interrupt;
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} else {
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ops->create_vcpu_thread = rr_start_vcpu_thread;
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ops->kick_vcpu_thread = rr_kick_vcpu_thread;
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if (icount_enabled()) {
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ops->handle_interrupt = icount_handle_interrupt;
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ops->get_virtual_clock = icount_get;
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ops->get_elapsed_ticks = icount_get;
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} else {
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ops->handle_interrupt = tcg_handle_interrupt;
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}
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}
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ops->supports_guest_debug = tcg_supports_guest_debug;
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ops->insert_breakpoint = tcg_insert_breakpoint;
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ops->remove_breakpoint = tcg_remove_breakpoint;
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ops->remove_all_breakpoints = tcg_remove_all_breakpoints;
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}
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static void tcg_accel_ops_class_init(ObjectClass *oc, void *data)
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{
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AccelOpsClass *ops = ACCEL_OPS_CLASS(oc);
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ops->ops_init = tcg_accel_ops_init;
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}
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static const TypeInfo tcg_accel_ops_type = {
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.name = ACCEL_OPS_NAME("tcg"),
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.parent = TYPE_ACCEL_OPS,
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.class_init = tcg_accel_ops_class_init,
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.abstract = true,
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};
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module_obj(ACCEL_OPS_NAME("tcg"));
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static void tcg_accel_ops_register_types(void)
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{
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type_register_static(&tcg_accel_ops_type);
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}
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type_init(tcg_accel_ops_register_types);
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