Alistair Francis ed5abf46b3 target/riscv: Correctly implement TSR trap ... As reported in: https://bugs.launchpad.net/qemu/+bug/1851939 we weren't correctly handling illegal instructions based on the value of MSTATUS_TSR and the current privledge level. This patch fixes the issue raised in the bug by raising an illegal instruction if TSR is set and we are in S-Mode. Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Jonathan Behrens <jonathan@fintelia.io Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>		2020-03-16 17:03:13 -07:00
..
alpha
arm	target/arm: kvm: Inject events at the last stage of sync	2020-03-12 16:31:10 +00:00
cris
hppa	target/hppa: Allow, but diagnose, LDCW aligned only mod 4	2020-01-27 10:49:51 -08:00
i386	Merge branch 'exec_rw_const_v4' of https://github.com/philmd/qemu into HEAD	2020-02-25 13:41:48 +01:00
lm32
m68k
microblaze	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
mips	target/mips: Separate FPU-related helpers into their own file	2020-02-04 08:53:54 +01:00
moxie
nios2	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
openrisc
ppc	target/ppc/cpu.h: Clean up comments in the struct CPUPPCState definition	2020-02-21 09:15:04 +11:00
riscv	target/riscv: Correctly implement TSR trap	2020-03-16 17:03:13 -07:00
s390x	s390x: ipl: Consolidate iplb validity check into one function	2020-03-10 10:18:20 +01:00
sh4
sparc	qdev: set properties with device_class_set_props()	2020-01-24 20:59:15 +01:00
tilegx
tricore
unicore32
xtensa