237 lines
6.7 KiB
C
237 lines
6.7 KiB
C
/*
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* QEMU monitor for RISC-V
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*
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* Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com>
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*
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* RISC-V specific monitor commands implementation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2 or later, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "cpu.h"
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#include "cpu_bits.h"
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#include "monitor/monitor.h"
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#include "monitor/hmp-target.h"
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#ifdef TARGET_RISCV64
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#define PTE_HEADER_FIELDS "vaddr paddr "\
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"size attr\n"
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#define PTE_HEADER_DELIMITER "---------------- ---------------- "\
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"---------------- -------\n"
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#else
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#define PTE_HEADER_FIELDS "vaddr paddr size attr\n"
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#define PTE_HEADER_DELIMITER "-------- ---------------- -------- -------\n"
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#endif
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/* Perform linear address sign extension */
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static target_ulong addr_canonical(int va_bits, target_ulong addr)
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{
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#ifdef TARGET_RISCV64
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if (addr & (1UL << (va_bits - 1))) {
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addr |= (hwaddr)-(1L << va_bits);
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}
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#endif
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return addr;
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}
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static void print_pte_header(Monitor *mon)
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{
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monitor_printf(mon, PTE_HEADER_FIELDS);
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monitor_printf(mon, PTE_HEADER_DELIMITER);
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}
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static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr,
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hwaddr paddr, target_ulong size, int attr)
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{
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/* santity check on vaddr */
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if (vaddr >= (1UL << va_bits)) {
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return;
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}
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if (!size) {
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return;
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}
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monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx
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" %c%c%c%c%c%c%c\n",
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addr_canonical(va_bits, vaddr),
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paddr, size,
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attr & PTE_R ? 'r' : '-',
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attr & PTE_W ? 'w' : '-',
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attr & PTE_X ? 'x' : '-',
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attr & PTE_U ? 'u' : '-',
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attr & PTE_G ? 'g' : '-',
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attr & PTE_A ? 'a' : '-',
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attr & PTE_D ? 'd' : '-');
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}
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static void walk_pte(Monitor *mon, hwaddr base, target_ulong start,
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int level, int ptidxbits, int ptesize, int va_bits,
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target_ulong *vbase, hwaddr *pbase, hwaddr *last_paddr,
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target_ulong *last_size, int *last_attr)
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{
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hwaddr pte_addr;
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hwaddr paddr;
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target_ulong pgsize;
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target_ulong pte;
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int ptshift;
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int attr;
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int idx;
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if (level < 0) {
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return;
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}
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ptshift = level * ptidxbits;
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pgsize = 1UL << (PGSHIFT + ptshift);
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for (idx = 0; idx < (1UL << ptidxbits); idx++) {
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pte_addr = base + idx * ptesize;
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cpu_physical_memory_read(pte_addr, &pte, ptesize);
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paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT;
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attr = pte & 0xff;
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/* PTE has to be valid */
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if (attr & PTE_V) {
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if (attr & (PTE_R | PTE_W | PTE_X)) {
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/*
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* A leaf PTE has been found
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*
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* If current PTE's permission bits differ from the last one,
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* or current PTE's ppn does not make a contiguous physical
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* address block together with the last one, print out the last
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* contiguous mapped block details.
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*/
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if ((*last_attr != attr) ||
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(*last_paddr + *last_size != paddr)) {
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print_pte(mon, va_bits, *vbase, *pbase,
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*last_paddr + *last_size - *pbase, *last_attr);
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*vbase = start;
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*pbase = paddr;
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*last_attr = attr;
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}
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*last_paddr = paddr;
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*last_size = pgsize;
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} else {
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/* pointer to the next level of the page table */
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walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize,
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va_bits, vbase, pbase, last_paddr,
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last_size, last_attr);
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}
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}
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start += pgsize;
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}
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}
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static void mem_info_svxx(Monitor *mon, CPUArchState *env)
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{
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int levels, ptidxbits, ptesize, vm, va_bits;
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hwaddr base;
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target_ulong vbase;
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hwaddr pbase;
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hwaddr last_paddr;
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target_ulong last_size;
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int last_attr;
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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base = (hwaddr)get_field(env->satp, SATP32_PPN) << PGSHIFT;
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vm = get_field(env->satp, SATP32_MODE);
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} else {
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base = (hwaddr)get_field(env->satp, SATP64_PPN) << PGSHIFT;
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vm = get_field(env->satp, SATP64_MODE);
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}
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switch (vm) {
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case VM_1_10_SV32:
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levels = 2;
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ptidxbits = 10;
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ptesize = 4;
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break;
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case VM_1_10_SV39:
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levels = 3;
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ptidxbits = 9;
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ptesize = 8;
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break;
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case VM_1_10_SV48:
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levels = 4;
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ptidxbits = 9;
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ptesize = 8;
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break;
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case VM_1_10_SV57:
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levels = 5;
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ptidxbits = 9;
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ptesize = 8;
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break;
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default:
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g_assert_not_reached();
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break;
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}
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/* calculate virtual address bits */
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va_bits = PGSHIFT + levels * ptidxbits;
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/* print header */
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print_pte_header(mon);
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vbase = -1;
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pbase = -1;
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last_paddr = -1;
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last_size = 0;
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last_attr = 0;
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/* walk page tables, starting from address 0 */
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walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits,
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&vbase, &pbase, &last_paddr, &last_size, &last_attr);
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/* don't forget the last one */
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print_pte(mon, va_bits, vbase, pbase,
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last_paddr + last_size - pbase, last_attr);
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}
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void hmp_info_mem(Monitor *mon, const QDict *qdict)
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{
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CPUArchState *env;
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env = mon_get_cpu_env(mon);
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if (!env) {
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monitor_printf(mon, "No CPU available\n");
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return;
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}
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if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
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monitor_printf(mon, "S-mode MMU unavailable\n");
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return;
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}
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if (riscv_cpu_mxl(env) == MXL_RV32) {
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if (!(env->satp & SATP32_MODE)) {
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monitor_printf(mon, "No translation or protection\n");
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return;
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}
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} else {
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if (!(env->satp & SATP64_MODE)) {
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monitor_printf(mon, "No translation or protection\n");
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return;
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}
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}
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mem_info_svxx(mon, env);
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}
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