147 lines
4.1 KiB
C
147 lines
4.1 KiB
C
/*
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* Flush the host cpu caches.
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*/
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#include "qemu/osdep.h"
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#include "qemu/cacheflush.h"
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#include "qemu/bitops.h"
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#if defined(__i386__) || defined(__x86_64__) || defined(__s390__)
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/* Caches are coherent and do not require flushing; symbol inline. */
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#elif defined(__aarch64__)
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#ifdef CONFIG_DARWIN
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/* Apple does not expose CTR_EL0, so we must use system interfaces. */
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extern void sys_icache_invalidate(void *start, size_t len);
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extern void sys_dcache_flush(void *start, size_t len);
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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sys_dcache_flush((void *)rw, len);
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sys_icache_invalidate((void *)rx, len);
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}
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#else
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/*
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* TODO: unify this with cacheinfo.c.
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* We want to save the whole contents of CTR_EL0, so that we
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* have more than the linesize, but also IDC and DIC.
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*/
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static uint64_t save_ctr_el0;
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static void __attribute__((constructor)) init_ctr_el0(void)
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{
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asm volatile("mrs\t%0, ctr_el0" : "=r"(save_ctr_el0));
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}
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/*
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* This is a copy of gcc's __aarch64_sync_cache_range, modified
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* to fit this three-operand interface.
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*/
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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const unsigned CTR_IDC = 1u << 28;
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const unsigned CTR_DIC = 1u << 29;
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const uint64_t ctr_el0 = save_ctr_el0;
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const uintptr_t icache_lsize = 4 << extract64(ctr_el0, 0, 4);
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const uintptr_t dcache_lsize = 4 << extract64(ctr_el0, 16, 4);
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uintptr_t p;
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/*
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* If CTR_EL0.IDC is enabled, Data cache clean to the Point of Unification
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* is not required for instruction to data coherence.
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*/
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if (!(ctr_el0 & CTR_IDC)) {
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/*
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* Loop over the address range, clearing one cache line at once.
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* Data cache must be flushed to unification first to make sure
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* the instruction cache fetches the updated data.
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*/
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for (p = rw & -dcache_lsize; p < rw + len; p += dcache_lsize) {
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asm volatile("dc\tcvau, %0" : : "r" (p) : "memory");
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}
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asm volatile("dsb\tish" : : : "memory");
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}
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/*
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* If CTR_EL0.DIC is enabled, Instruction cache cleaning to the Point
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* of Unification is not required for instruction to data coherence.
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*/
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if (!(ctr_el0 & CTR_DIC)) {
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for (p = rx & -icache_lsize; p < rx + len; p += icache_lsize) {
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asm volatile("ic\tivau, %0" : : "r"(p) : "memory");
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}
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asm volatile ("dsb\tish" : : : "memory");
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}
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asm volatile("isb" : : : "memory");
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}
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#endif /* CONFIG_DARWIN */
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#elif defined(__mips__)
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#ifdef __OpenBSD__
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#include <machine/sysarch.h>
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#else
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#include <sys/cachectl.h>
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#endif
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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if (rx != rw) {
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cacheflush((void *)rw, len, DCACHE);
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}
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cacheflush((void *)rx, len, ICACHE);
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}
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#elif defined(__powerpc__)
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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uintptr_t p, b, e;
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size_t dsize = qemu_dcache_linesize;
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size_t isize = qemu_icache_linesize;
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b = rw & ~(dsize - 1);
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e = (rw + len + dsize - 1) & ~(dsize - 1);
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for (p = b; p < e; p += dsize) {
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asm volatile ("dcbst 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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b = rx & ~(isize - 1);
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e = (rx + len + isize - 1) & ~(isize - 1);
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for (p = b; p < e; p += isize) {
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asm volatile ("icbi 0,%0" : : "r"(p) : "memory");
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}
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asm volatile ("sync" : : : "memory");
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asm volatile ("isync" : : : "memory");
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}
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#elif defined(__sparc__)
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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/* No additional data flush to the RW virtual address required. */
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uintptr_t p, end = (rx + len + 7) & -8;
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for (p = rx & -8; p < end; p += 8) {
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__asm__ __volatile__("flush\t%0" : : "r" (p));
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}
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}
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#else
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void flush_idcache_range(uintptr_t rx, uintptr_t rw, size_t len)
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{
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if (rw != rx) {
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__builtin___clear_cache((char *)rw, (char *)rw + len);
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}
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__builtin___clear_cache((char *)rx, (char *)rx + len);
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}
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#endif
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