f5ae2a4fd8
s390 provides several CPU resets: - CPU reset, clears interrupts, stop processing, clears TLB, but does not touch registers - initial CPU reset, like CPU reset, but also clears PSW, prefix, FPC, timer and control registers. It does not touch gprs, fprs and acrs (!) - Power on reset: the full monty wire up CPUClass reset to the full monty, but provide the lesser resets as part of S390CPUClass. Signed-off-by: Christian Borntraeger <borntraeger@de.ibm.com>
251 lines
6.6 KiB
C
251 lines
6.6 KiB
C
/*
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* QEMU S/390 CPU
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*
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* Copyright (c) 2009 Ulrich Hecht
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* Copyright (c) 2011 Alexander Graf
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* Copyright (c) 2012 SUSE LINUX Products GmbH
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* Copyright (c) 2012 IBM Corp.
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see
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* <http://www.gnu.org/licenses/lgpl-2.1.html>
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* Contributions after 2012-12-11 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*/
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#include "cpu.h"
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#include "qemu-common.h"
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#include "qemu/timer.h"
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#include "hw/hw.h"
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#ifndef CONFIG_USER_ONLY
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#include "sysemu/arch_init.h"
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#endif
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#define CR0_RESET 0xE0UL
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#define CR14_RESET 0xC2000000UL;
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/* generate CPU information for cpu -? */
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void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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#ifdef CONFIG_KVM
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(*cpu_fprintf)(f, "s390 %16s\n", "host");
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#endif
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}
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#ifndef CONFIG_USER_ONLY
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CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
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{
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CpuDefinitionInfoList *entry;
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CpuDefinitionInfo *info;
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info = g_malloc0(sizeof(*info));
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info->name = g_strdup("host");
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entry = g_malloc0(sizeof(*entry));
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entry->value = info;
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return entry;
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}
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#endif
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static void s390_cpu_set_pc(CPUState *cs, vaddr value)
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{
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S390CPU *cpu = S390_CPU(cs);
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cpu->env.psw.addr = value;
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}
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#if !defined(CONFIG_USER_ONLY)
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/* S390CPUClass::load_normal() */
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static void s390_cpu_load_normal(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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cpu->env.psw.addr = ldl_phys(4) & PSW_MASK_ESA_ADDR;
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cpu->env.psw.mask = PSW_MASK_32 | PSW_MASK_64;
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s390_add_running_cpu(cpu);
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}
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#endif
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/* S390CPUClass::cpu_reset() */
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static void s390_cpu_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUS390XState *env = &cpu->env;
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s390_del_running_cpu(cpu);
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scc->parent_reset(s);
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#if !defined(CONFIG_USER_ONLY)
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s->halted = 1;
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#endif
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tlb_flush(env, 1);
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}
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/* S390CPUClass::initial_reset() */
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static void s390_cpu_initial_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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CPUS390XState *env = &cpu->env;
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s390_cpu_reset(s);
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/* initial reset does not touch regs,fregs and aregs */
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memset(&env->fpc, 0, offsetof(CPUS390XState, breakpoints) -
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offsetof(CPUS390XState, fpc));
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/* architectured initial values for CR 0 and 14 */
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env->cregs[0] = CR0_RESET;
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env->cregs[14] = CR14_RESET;
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}
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/* CPUClass:reset() */
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static void s390_cpu_full_reset(CPUState *s)
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{
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S390CPU *cpu = S390_CPU(s);
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S390CPUClass *scc = S390_CPU_GET_CLASS(cpu);
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CPUS390XState *env = &cpu->env;
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s390_del_running_cpu(cpu);
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scc->parent_reset(s);
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memset(env, 0, offsetof(CPUS390XState, breakpoints));
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/* architectured initial values for CR 0 and 14 */
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env->cregs[0] = CR0_RESET;
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env->cregs[14] = CR14_RESET;
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/* set halted to 1 to make sure we can add the cpu in
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* s390_ipl_cpu code, where CPUState::halted is set back to 0
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* after incrementing the cpu counter */
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#if !defined(CONFIG_USER_ONLY)
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s->halted = 1;
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#endif
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tlb_flush(env, 1);
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}
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#if !defined(CONFIG_USER_ONLY)
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static void s390_cpu_machine_reset_cb(void *opaque)
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{
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S390CPU *cpu = opaque;
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cpu_reset(CPU(cpu));
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}
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#endif
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static void s390_cpu_realizefn(DeviceState *dev, Error **errp)
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{
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CPUState *cs = CPU(dev);
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S390CPUClass *scc = S390_CPU_GET_CLASS(dev);
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qemu_init_vcpu(cs);
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cpu_reset(cs);
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scc->parent_realize(dev, errp);
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}
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static void s390_cpu_initfn(Object *obj)
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{
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CPUState *cs = CPU(obj);
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S390CPU *cpu = S390_CPU(obj);
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CPUS390XState *env = &cpu->env;
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static bool inited;
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static int cpu_num = 0;
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#if !defined(CONFIG_USER_ONLY)
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struct tm tm;
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#endif
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cs->env_ptr = env;
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cpu_exec_init(env);
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#if !defined(CONFIG_USER_ONLY)
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qemu_register_reset(s390_cpu_machine_reset_cb, cpu);
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qemu_get_timedate(&tm, 0);
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env->tod_offset = TOD_UNIX_EPOCH +
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(time2tod(mktimegm(&tm)) * 1000000000ULL);
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env->tod_basetime = 0;
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env->tod_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_tod_timer, cpu);
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env->cpu_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, s390x_cpu_timer, cpu);
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/* set CPUState::halted state to 1 to avoid decrementing the running
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* cpu counter in s390_cpu_reset to a negative number at
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* initial ipl */
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cs->halted = 1;
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#endif
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env->cpu_num = cpu_num++;
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env->ext_index = -1;
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if (tcg_enabled() && !inited) {
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inited = true;
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s390x_translate_init();
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}
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}
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static void s390_cpu_finalize(Object *obj)
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{
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#if !defined(CONFIG_USER_ONLY)
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S390CPU *cpu = S390_CPU(obj);
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qemu_unregister_reset(s390_cpu_machine_reset_cb, cpu);
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#endif
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}
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static const VMStateDescription vmstate_s390_cpu = {
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.name = "cpu",
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.unmigratable = 1,
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};
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static void s390_cpu_class_init(ObjectClass *oc, void *data)
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{
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S390CPUClass *scc = S390_CPU_CLASS(oc);
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CPUClass *cc = CPU_CLASS(scc);
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DeviceClass *dc = DEVICE_CLASS(oc);
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scc->parent_realize = dc->realize;
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dc->realize = s390_cpu_realizefn;
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scc->parent_reset = cc->reset;
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#if !defined(CONFIG_USER_ONLY)
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scc->load_normal = s390_cpu_load_normal;
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#endif
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scc->cpu_reset = s390_cpu_reset;
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scc->initial_cpu_reset = s390_cpu_initial_reset;
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cc->reset = s390_cpu_full_reset;
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cc->do_interrupt = s390_cpu_do_interrupt;
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cc->dump_state = s390_cpu_dump_state;
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cc->set_pc = s390_cpu_set_pc;
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cc->gdb_read_register = s390_cpu_gdb_read_register;
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cc->gdb_write_register = s390_cpu_gdb_write_register;
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#ifndef CONFIG_USER_ONLY
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cc->get_phys_page_debug = s390_cpu_get_phys_page_debug;
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cc->write_elf64_note = s390_cpu_write_elf64_note;
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cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote;
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#endif
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dc->vmsd = &vmstate_s390_cpu;
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cc->gdb_num_core_regs = S390_NUM_REGS;
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}
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static const TypeInfo s390_cpu_type_info = {
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.name = TYPE_S390_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(S390CPU),
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.instance_init = s390_cpu_initfn,
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.instance_finalize = s390_cpu_finalize,
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.abstract = false,
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.class_size = sizeof(S390CPUClass),
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.class_init = s390_cpu_class_init,
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};
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static void s390_cpu_register_types(void)
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{
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type_register_static(&s390_cpu_type_info);
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}
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type_init(s390_cpu_register_types)
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