8b17de88e0
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4007 c046a42c-6fe2-441c-8c8c-71466251a162
83 lines
3.2 KiB
C
83 lines
3.2 KiB
C
#ifndef SUN4M_H
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#define SUN4M_H
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/* Devices used by sparc32 system. */
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/* iommu.c */
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void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq);
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void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int is_write);
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static inline void sparc_iommu_memory_read(void *opaque,
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target_phys_addr_t addr,
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uint8_t *buf, int len)
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{
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sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
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}
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static inline void sparc_iommu_memory_write(void *opaque,
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target_phys_addr_t addr,
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uint8_t *buf, int len)
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{
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sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
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}
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/* tcx.c */
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void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
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unsigned long vram_offset, int vram_size, int width, int height,
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int depth);
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/* slavio_intctl.c */
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void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
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const uint32_t *intbit_to_level,
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qemu_irq **irq, qemu_irq **cpu_irq,
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qemu_irq **parent_irq, unsigned int cputimer);
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void slavio_pic_info(void *opaque);
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void slavio_irq_info(void *opaque);
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/* sbi.c */
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void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
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qemu_irq **parent_irq);
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/* sun4c_intctl.c */
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void *sun4c_intctl_init(target_phys_addr_t addr, qemu_irq **irq,
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qemu_irq *parent_irq);
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/* slavio_timer.c */
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void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
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qemu_irq *cpu_irqs, unsigned int num_cpus);
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/* slavio_serial.c */
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SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
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CharDriverState *chr1, CharDriverState *chr2);
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void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq,
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int disabled);
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/* slavio_misc.c */
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void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
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target_phys_addr_t aux1_base,
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target_phys_addr_t aux2_base, qemu_irq irq,
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CPUState *env);
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void slavio_set_power_fail(void *opaque, int power_failing);
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/* cs4231.c */
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void cs_init(target_phys_addr_t base, int irq, void *intctl);
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/* sparc32_dma.c */
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void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
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void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
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void ledma_memory_read(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int do_bswap);
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void ledma_memory_write(void *opaque, target_phys_addr_t addr,
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uint8_t *buf, int len, int do_bswap);
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void espdma_memory_read(void *opaque, uint8_t *buf, int len);
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void espdma_memory_write(void *opaque, uint8_t *buf, int len);
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/* pcnet.c */
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void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
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qemu_irq irq, qemu_irq *reset);
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/* eccmemctl.c */
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void *ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version);
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#endif
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