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b96ac3e4cc
qemu-e2k/target-xtensa
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Max Filippov b96ac3e4cc target-xtensa: define TLB_TEMPLATE for MMU-less cores 
TLB_TEMPLATE macro specifies TLB geometry in the core configuration.
Make TLB_TEMPLATE available for region protection core variants,
defining 1 way ITLB and DTLB with 8 entries each.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
2012-02-18 01:25:27 +04:00
..
core-dc232b target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
core-dc232b.c target-xtensa: add dc232b core 2011-10-16 10:40:02 +00:00
core-fsf.c target-xtensa: add fsf core 2011-10-16 10:40:16 +00:00
cpu.h target-xtensa: extract core configuration from overlay 2011-10-16 10:39:52 +00:00
helper.c target-xtensa: fix MMUv3 initialization 2011-11-26 09:44:34 +00:00
helpers.h target-xtensa: implement memory protection options 2011-09-10 16:57:40 +00:00
machine.c
op_helper.c target-xtensa: fix guest hang on masked CCOMPARE interrupt 2011-10-15 21:03:03 +00:00
overlay_tool.h target-xtensa: define TLB_TEMPLATE for MMU-less cores 2012-02-18 01:25:27 +04:00
translate.c target-xtensa: raise an exception for invalid and reserved opcodes 2011-11-02 05:05:52 +04:00