ecf2864784
Generate SMBIOS tables for the RISC-V mach-virt.
Add CONFIG_SMBIOS=y to the RISC-V default config.
Set the default processor family in the type 4 table.
The implementation is based on the corresponding ARM and Loongson code.
With the patch the following firmware tables are provided:
etc/smbios/smbios-anchor
etc/smbios/smbios-tables
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Message-ID: <20240123184229.10415-4-heinrich.schuchardt@canonical.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
90 lines
1.6 KiB
Plaintext
90 lines
1.6 KiB
Plaintext
config RISCV_NUMA
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bool
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config IBEX
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bool
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# RISC-V machines in alphabetical order
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config MICROCHIP_PFSOC
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bool
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select CADENCE_SDHCI
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select MCHP_PFSOC_DMC
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select MCHP_PFSOC_IOSCB
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select MCHP_PFSOC_MMUART
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select MCHP_PFSOC_SYSREG
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select RISCV_ACLINT
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select UNIMP
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config OPENTITAN
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bool
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select IBEX
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select SIFIVE_PLIC
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select UNIMP
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config RISCV_VIRT
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bool
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imply PCI_DEVICES
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imply VIRTIO_VGA
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imply TEST_DEVICES
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imply TPM_TIS_SYSBUS
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select RISCV_NUMA
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select GOLDFISH_RTC
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select PCI
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select PCI_EXPRESS_GENERIC_BRIDGE
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select PFLASH_CFI01
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select SERIAL
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select RISCV_ACLINT
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select RISCV_APLIC
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select RISCV_IMSIC
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select SIFIVE_PLIC
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select SIFIVE_TEST
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select SMBIOS
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select VIRTIO_MMIO
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select FW_CFG_DMA
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select PLATFORM_BUS
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select ACPI
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select ACPI_PCI
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config SHAKTI_C
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bool
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select RISCV_ACLINT
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select SHAKTI_UART
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select SIFIVE_PLIC
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select UNIMP
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config SIFIVE_E
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bool
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select RISCV_ACLINT
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select SIFIVE_GPIO
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select SIFIVE_PLIC
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select SIFIVE_UART
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select SIFIVE_E_PRCI
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select SIFIVE_E_AON
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select UNIMP
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config SIFIVE_U
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bool
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select CADENCE
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select RISCV_ACLINT
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select SIFIVE_GPIO
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select SIFIVE_PDMA
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select SIFIVE_PLIC
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select SIFIVE_SPI
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select SIFIVE_UART
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select SIFIVE_U_OTP
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select SIFIVE_U_PRCI
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select SIFIVE_PWM
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select SSI_M25P80
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select SSI_SD
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select UNIMP
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config SPIKE
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bool
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select RISCV_NUMA
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select HTIF
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select RISCV_ACLINT
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select SIFIVE_PLIC
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