Marcin Nowakowski baf21eebc3 target/mips: enable GINVx support for I6400 and I6500 ... GINVI and GINVT operations are supported on MIPS I6400 and I6500 cores, so indicate that properly in CP0.Config5 register bits [16:15]. Cc: qemu-stable@nongnu.org Signed-off-by: Marcin Nowakowski <marcin.nowakowski@fungible.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-Id: <20230630072806.3093704-1-marcin.nowakowski@fungible.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>		2023-07-10 23:33:38 +02:00
..
sysemu	target/mips: Rework cp0_timer with clock API	2023-07-10 21:53:03 +02:00
tcg	target/mips/mxu: Add Q8SAD instruction	2023-07-10 23:33:38 +02:00
cpu-defs.c.inc	target/mips: enable GINVx support for I6400 and I6500	2023-07-10 23:33:38 +02:00
cpu-param.h	target/mips: Remove NB_MMU_MODES define	2023-03-13 06:44:37 -07:00
cpu-qom.h
cpu.c	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
cpu.h	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
fpu_helper.h
fpu.c
gdbstub.c
helper.h	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
internal.h	target/mips: Implement Loongson CSR instructions	2023-07-10 23:33:37 +02:00
Kconfig
kvm_mips.h
kvm.c
meson.build	meson: Replace softmmu_ss -> system_ss	2023-06-20 10:01:30 +02:00
mips-defs.h
msa.c