Richard Henderson bbad7c62d4 target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state ... We do not need to compute any of these values for M-profile. Further, XSCALE_CPAR overlaps VECSTRIDE so obviously the two sets must be mutually exclusive. Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191023150057.25731-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>		2019-10-24 17:16:27 +01:00
..
alpha	target/alpha: Tidy helper_fp_exc_raise_s	2019-09-26 19:00:53 +01:00
arm	target/arm: Hoist XSCALE_CPAR, VECLEN, VECSTRIDE in cpu_get_tb_cpu_state	2019-10-24 17:16:27 +01:00
cris
hppa
i386	target/i386: Introduce Denverton CPU model	2019-10-23 23:37:42 -03:00
lm32
m68k	target/m68k/fpu_helper.c: rename the access arguments	2019-09-19 12:12:19 +02:00
microblaze
mips	target/mips: msa: Move helpers for <AND|NOR|OR|XOR>.V	2019-10-01 16:58:45 +02:00
moxie
nios2
openrisc
ppc	target/ppc: Fix for optimized vsl/vsr instructions	2019-10-24 09:36:55 +11:00
riscv	gdbstub: riscv: fix the fflags registers	2019-09-17 08:42:50 -07:00
s390x	s390x/kvm: Set default cpu model for all machine classes	2019-10-21 18:03:08 +02:00
sh4
sparc
tilegx
tricore
unicore32
xtensa	target/xtensa: regenerate and re-import test_mmuhifi_c3 core	2019-10-18 19:54:27 -07:00