qemu-e2k/hw/riscv
Cédric Le Goater c3287c0f70 hw/sd: Introduce a "sd-card" SPI variant model
and replace the SDState::spi attribute with a test checking the
SDProto array of commands.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Cédric Le Goater <clg@kaod.org>
2023-09-01 11:40:04 +02:00
..
boot.c hw/riscv/boot.c: make riscv_load_initrd() static 2023-02-16 07:55:37 -08:00
Kconfig hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. 2023-07-10 22:29:15 +10:00
meson.build hw/riscv/virt: Enable basic ACPI infrastructure 2023-03-06 11:35:04 -08:00
microchip_pfsoc.c
numa.c hw/riscv: Fix typo field in error_report 2023-07-19 14:31:41 +10:00
opentitan.c hw/riscv/opentitan: Correct OpenTitanState parent type/size 2023-06-13 17:19:42 +10:00
riscv_hart.c
shakti_c.c *: Add missing includes of qemu/error-report.h 2023-03-22 15:06:57 +00:00
sifive_e.c hw/riscv: sifive_e: Support the watchdog timer of HiFive 1 rev b. 2023-07-10 22:29:15 +10:00
sifive_u.c hw/sd: Introduce a "sd-card" SPI variant model 2023-09-01 11:40:04 +02:00
spike.c hw/riscv: Validate cluster and NUMA node boundary 2023-06-26 10:23:01 +02:00
virt-acpi-build.c *: Add missing includes of qemu/error-report.h 2023-03-22 15:06:57 +00:00
virt.c hw/riscv/virt.c: change 'aclint' TCG check 2023-08-11 14:16:26 -04:00