Yueh-Ting (eop) Chen 8ff8ac6329 target/riscv: rvv: Add missing early exit condition for whole register load/store ... According to v-spec (section 7.9): The instructions operate with an effective vector length, evl=NFIELDS*VLEN/EEW, regardless of current settings in vtype and vl. The usual property that no elements are written if vstart ≥ vl does not apply to these instructions. Instead, no elements are written if vstart ≥ evl. Signed-off-by: eop Chen <eop.chen@sifive.com> Reviewed-by: Frank Chang <frank.chang@sifive.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <164762720573.18409.3931931227997483525-0@git.sr.ht> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2022-04-01 08:40:55 +10:00
..
trans_privileged.c.inc	target/riscv: Sign extend pc for different XLEN	2022-01-21 15:52:57 +10:00
trans_rva.c.inc	target/riscv: Calculate address according to XLEN	2022-01-21 15:52:57 +10:00
trans_rvb.c.inc	target/riscv: fix inverted checks for ext_zb[abcs]	2022-03-03 13:14:50 +10:00
trans_rvd.c.inc	target/riscv: add support for zdinx	2022-03-03 13:14:50 +10:00
trans_rvf.c.inc	target/riscv: add support for zfinx	2022-03-03 13:14:50 +10:00
trans_rvh.c.inc	exec/memop: Adding signedness to quad definitions	2022-01-08 15:46:10 +10:00
trans_rvi.c.inc	target/riscv: access configuration through cfg_ptr in DisasContext	2022-02-16 12:24:18 +10:00
trans_rvm.c.inc	target/riscv: support for 128-bit M extension	2022-01-08 15:46:10 +10:00
trans_rvv.c.inc	target/riscv: rvv: Add missing early exit condition for whole register load/store	2022-04-01 08:40:55 +10:00
trans_rvzfh.c.inc	target/riscv: add support for zhinx/zhinxmin	2022-03-03 13:14:50 +10:00
trans_svinval.c.inc	target/riscv: add support for svinval extension	2022-02-16 12:25:52 +10:00
trans_xventanacondops.c.inc	target/riscv: Add XVentanaCondOps custom extension	2022-02-16 12:24:18 +10:00