Daniel Henrique Barboza bd2c82283d target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ() ... Calculate the maximum vector size possible, 'max_sz', which is the size in bytes 'vlenb' multiplied by the max value of LMUL (LMUL = 8, when s->lmul = 3). 'max_sz' is then shifted right by 'scale', expressed as '3 - s->lmul', which is clearer than doing 'scale = lmul - 3' and then using '-scale' in the shift right. Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-ID: <20240122161107.26737-10-dbarboza@ventanamicro.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com>		2024-02-09 20:43:14 +10:00
..
insn_trans	target/riscv/insn_trans/trans_rvv.c.inc: use 'vlenb' in MAXSZ()	2024-02-09 20:43:14 +10:00
kvm	target/riscv: remove riscv_cpu_options[]	2024-02-09 11:13:08 +10:00
tcg	target/riscv: remove riscv_cpu_options[]	2024-02-09 11:13:08 +10:00
arch_dump.c
bitmanip_helper.c
common-semi-target.h
cpu_bits.h	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
cpu_cfg.h	target/riscv: add 'vlenb' field in cpu->cfg	2024-02-09 20:41:59 +10:00
cpu_helper.c	target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index	2024-02-03 16:46:10 +10:00
cpu_user.h
cpu_vendorid.h
cpu-param.h
cpu-qom.h	target/riscv: add rva22s64 cpu	2024-01-10 18:47:47 +10:00
cpu.c	target/riscv: add 'vlenb' field in cpu->cfg	2024-02-09 20:41:59 +10:00
cpu.h	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
crypto_helper.c
csr.c	target/riscv/csr.c: use 'vlenb' instead of 'vlen'	2024-02-09 20:43:14 +10:00
debug.c	target/riscv: Implement optional CSR mcontext of debug Sdtrig extension	2024-02-09 20:40:32 +10:00
debug.h
fpu_helper.c
gdbstub.c	target/riscv/gdbstub.c: use 'vlenb' instead of shifting 'vlen'	2024-02-09 20:43:14 +10:00
helper.h
insn16.decode
insn32.decode	target/riscv: Add support for Zacas extension	2024-01-10 18:47:47 +10:00
instmap.h
internals.h	target/riscv: Use env_archcpu() in [check_]nanbox()	2023-11-07 12:13:27 +01:00
Kconfig
m128_helper.c
machine.c	target/riscv: Constify VMState in machine.c	2023-12-29 11:17:30 +11:00
meson.build
monitor.c
op_helper.c	target/riscv: Replace cpu_mmu_index with riscv_env_mmu_index	2024-02-03 16:46:10 +10:00
pmp.c	target/riscv: pmp: Ignore writes when RW=01 and MML=0	2024-01-10 18:47:47 +10:00
pmp.h	target/riscv/pmp: Use hwaddr instead of target_ulong for RV32	2024-01-10 18:47:46 +10:00
pmu.c	target/riscv: Add "pmu-mask" property to replace "pmu-num"	2023-11-07 11:06:02 +10:00
pmu.h	target/riscv: Use existing PMU counter mask in FDT generation	2023-11-07 11:06:02 +10:00
riscv-qmp-cmds.c	riscv-qmp-cmds.c: add profile flags in cpu-model-expansion	2024-01-10 18:47:47 +10:00
sbi_ecall_interface.h
time_helper.c
time_helper.h
trace-events
trace.h
translate.c	target: Use vaddr in gen_intermediate_code	2024-01-29 07:06:03 +10:00
vcrypto_helper.c
vector_helper.c	target/riscv/vector_helper.c: use vlenb in HELPER(vsetvl)	2024-02-09 20:43:14 +10:00
vector_internals.c	riscv: Clean up includes	2024-01-30 21:20:20 +03:00
vector_internals.h	riscv: Clean up includes	2024-01-30 21:20:20 +03:00
xthead.decode
XVentanaCondOps.decode
zce_helper.c