bd57fb91ae
- BZ (comparison to zero); - BI0 (comparison to signed immediate); - BI1 (comparison to unsigned immediate); - B (two registers comparison, bit sets comparison); - BEQZ.N/BNEZ.N (narrow comparison to zero). Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
758 lines
20 KiB
C
758 lines
20 KiB
C
/*
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* Xtensa ISA:
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* http://www.tensilica.com/products/literature-docs/documentation/xtensa-isa-databook.htm
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*
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* Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
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#include "tcg-op.h"
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#include "qemu-log.h"
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#include "helpers.h"
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#define GEN_HELPER 1
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#include "helpers.h"
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typedef struct DisasContext {
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const XtensaConfig *config;
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TranslationBlock *tb;
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uint32_t pc;
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uint32_t next_pc;
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int is_jmp;
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int singlestep_enabled;
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} DisasContext;
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static TCGv_ptr cpu_env;
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static TCGv_i32 cpu_pc;
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static TCGv_i32 cpu_R[16];
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#include "gen-icount.h"
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void xtensa_translate_init(void)
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{
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static const char * const regnames[] = {
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"ar0", "ar1", "ar2", "ar3",
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"ar4", "ar5", "ar6", "ar7",
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"ar8", "ar9", "ar10", "ar11",
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"ar12", "ar13", "ar14", "ar15",
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};
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int i;
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cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
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cpu_pc = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, pc), "pc");
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for (i = 0; i < 16; i++) {
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cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
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offsetof(CPUState, regs[i]),
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regnames[i]);
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}
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#define GEN_HELPER 2
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#include "helpers.h"
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}
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static inline bool option_enabled(DisasContext *dc, int opt)
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{
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return xtensa_option_enabled(dc->config, opt);
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}
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static void gen_exception(int excp)
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{
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TCGv_i32 tmp = tcg_const_i32(excp);
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gen_helper_exception(tmp);
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tcg_temp_free(tmp);
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}
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static void gen_jump_slot(DisasContext *dc, TCGv dest, int slot)
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{
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tcg_gen_mov_i32(cpu_pc, dest);
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if (dc->singlestep_enabled) {
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gen_exception(EXCP_DEBUG);
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} else {
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if (slot >= 0) {
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tcg_gen_goto_tb(slot);
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tcg_gen_exit_tb((tcg_target_long)dc->tb + slot);
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} else {
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tcg_gen_exit_tb(0);
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}
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}
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dc->is_jmp = DISAS_UPDATE;
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}
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static void gen_jump(DisasContext *dc, TCGv dest)
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{
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gen_jump_slot(dc, dest, -1);
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}
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static void gen_jumpi(DisasContext *dc, uint32_t dest, int slot)
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{
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TCGv_i32 tmp = tcg_const_i32(dest);
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if (((dc->pc ^ dest) & TARGET_PAGE_MASK) != 0) {
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slot = -1;
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}
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gen_jump_slot(dc, tmp, slot);
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tcg_temp_free(tmp);
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}
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static void gen_brcond(DisasContext *dc, TCGCond cond,
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TCGv_i32 t0, TCGv_i32 t1, uint32_t offset)
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{
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int label = gen_new_label();
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tcg_gen_brcond_i32(cond, t0, t1, label);
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gen_jumpi(dc, dc->next_pc, 0);
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gen_set_label(label);
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gen_jumpi(dc, dc->pc + offset, 1);
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}
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static void gen_brcondi(DisasContext *dc, TCGCond cond,
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TCGv_i32 t0, uint32_t t1, uint32_t offset)
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{
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TCGv_i32 tmp = tcg_const_i32(t1);
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gen_brcond(dc, cond, t0, tmp, offset);
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tcg_temp_free(tmp);
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}
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static void disas_xtensa_insn(DisasContext *dc)
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{
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#define HAS_OPTION(opt) do { \
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if (!option_enabled(dc, opt)) { \
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qemu_log("Option %d is not enabled %s:%d\n", \
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(opt), __FILE__, __LINE__); \
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goto invalid_opcode; \
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} \
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} while (0)
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#ifdef TARGET_WORDS_BIGENDIAN
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#define OP0 (((b0) & 0xf0) >> 4)
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#define OP1 (((b2) & 0xf0) >> 4)
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#define OP2 ((b2) & 0xf)
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#define RRR_R ((b1) & 0xf)
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#define RRR_S (((b1) & 0xf0) >> 4)
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#define RRR_T ((b0) & 0xf)
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#else
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#define OP0 (((b0) & 0xf))
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#define OP1 (((b2) & 0xf))
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#define OP2 (((b2) & 0xf0) >> 4)
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#define RRR_R (((b1) & 0xf0) >> 4)
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#define RRR_S (((b1) & 0xf))
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#define RRR_T (((b0) & 0xf0) >> 4)
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#endif
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#define RRRN_R RRR_R
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#define RRRN_S RRR_S
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#define RRRN_T RRR_T
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#define RRI8_R RRR_R
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#define RRI8_S RRR_S
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#define RRI8_T RRR_T
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#define RRI8_IMM8 (b2)
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#define RRI8_IMM8_SE ((((b2) & 0x80) ? 0xffffff00 : 0) | RRI8_IMM8)
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#ifdef TARGET_WORDS_BIGENDIAN
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#define RI16_IMM16 (((b1) << 8) | (b2))
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#else
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#define RI16_IMM16 (((b2) << 8) | (b1))
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#endif
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#ifdef TARGET_WORDS_BIGENDIAN
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#define CALL_N (((b0) & 0xc) >> 2)
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#define CALL_OFFSET ((((b0) & 0x3) << 16) | ((b1) << 8) | (b2))
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#else
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#define CALL_N (((b0) & 0x30) >> 4)
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#define CALL_OFFSET ((((b0) & 0xc0) >> 6) | ((b1) << 2) | ((b2) << 10))
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#endif
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#define CALL_OFFSET_SE \
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(((CALL_OFFSET & 0x20000) ? 0xfffc0000 : 0) | CALL_OFFSET)
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#define CALLX_N CALL_N
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#ifdef TARGET_WORDS_BIGENDIAN
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#define CALLX_M ((b0) & 0x3)
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#else
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#define CALLX_M (((b0) & 0xc0) >> 6)
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#endif
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#define CALLX_S RRR_S
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#define BRI12_M CALLX_M
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#define BRI12_S RRR_S
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BRI12_IMM12 ((((b1) & 0xf) << 8) | (b2))
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#else
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#define BRI12_IMM12 ((((b1) & 0xf0) >> 4) | ((b2) << 4))
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#endif
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#define BRI12_IMM12_SE (((BRI12_IMM12 & 0x800) ? 0xfffff000 : 0) | BRI12_IMM12)
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#define BRI8_M BRI12_M
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#define BRI8_R RRI8_R
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#define BRI8_S RRI8_S
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#define BRI8_IMM8 RRI8_IMM8
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#define BRI8_IMM8_SE RRI8_IMM8_SE
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#define RSR_SR (b1)
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uint8_t b0 = ldub_code(dc->pc);
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uint8_t b1 = ldub_code(dc->pc + 1);
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uint8_t b2 = ldub_code(dc->pc + 2);
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static const uint32_t B4CONST[] = {
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0xffffffff, 1, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
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};
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static const uint32_t B4CONSTU[] = {
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32768, 65536, 2, 3, 4, 5, 6, 7, 8, 10, 12, 16, 32, 64, 128, 256
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};
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if (OP0 >= 8) {
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dc->next_pc = dc->pc + 2;
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HAS_OPTION(XTENSA_OPTION_CODE_DENSITY);
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} else {
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dc->next_pc = dc->pc + 3;
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}
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switch (OP0) {
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case 0: /*QRST*/
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switch (OP1) {
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case 0: /*RST0*/
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switch (OP2) {
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case 0: /*ST0*/
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if ((RRR_R & 0xc) == 0x8) {
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HAS_OPTION(XTENSA_OPTION_BOOLEAN);
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}
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switch (RRR_R) {
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case 0: /*SNM0*/
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break;
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case 1: /*MOVSPw*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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break;
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case 2: /*SYNC*/
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break;
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case 3:
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break;
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}
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break;
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case 1: /*AND*/
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tcg_gen_and_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
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break;
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case 2: /*OR*/
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tcg_gen_or_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
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break;
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case 3: /*XOR*/
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tcg_gen_xor_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
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break;
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case 4: /*ST1*/
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break;
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case 5: /*TLB*/
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break;
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case 6: /*RT0*/
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switch (RRR_S) {
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case 0: /*NEG*/
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tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
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break;
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case 1: /*ABS*/
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{
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int label = gen_new_label();
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tcg_gen_mov_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
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tcg_gen_brcondi_i32(
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TCG_COND_GE, cpu_R[RRR_R], 0, label);
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tcg_gen_neg_i32(cpu_R[RRR_R], cpu_R[RRR_T]);
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gen_set_label(label);
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}
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break;
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default: /*reserved*/
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break;
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}
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break;
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case 7: /*reserved*/
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break;
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case 8: /*ADD*/
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tcg_gen_add_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
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break;
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case 9: /*ADD**/
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case 10:
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case 11:
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 8);
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tcg_gen_add_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
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tcg_temp_free(tmp);
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}
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break;
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case 12: /*SUB*/
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tcg_gen_sub_i32(cpu_R[RRR_R], cpu_R[RRR_S], cpu_R[RRR_T]);
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break;
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case 13: /*SUB**/
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case 14:
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case 15:
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_shli_i32(tmp, cpu_R[RRR_S], OP2 - 12);
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tcg_gen_sub_i32(cpu_R[RRR_R], tmp, cpu_R[RRR_T]);
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tcg_temp_free(tmp);
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}
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break;
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}
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break;
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case 1: /*RST1*/
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break;
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case 2: /*RST2*/
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break;
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case 3: /*RST3*/
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break;
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case 4: /*EXTUI*/
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case 5:
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break;
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case 6: /*CUST0*/
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break;
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case 7: /*CUST1*/
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break;
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case 8: /*LSCXp*/
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HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
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break;
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case 9: /*LSC4*/
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break;
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case 10: /*FP0*/
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HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
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break;
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case 11: /*FP1*/
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HAS_OPTION(XTENSA_OPTION_FP_COPROCESSOR);
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break;
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default: /*reserved*/
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break;
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}
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break;
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case 1: /*L32R*/
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{
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TCGv_i32 tmp = tcg_const_i32(
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(0xfffc0000 | (RI16_IMM16 << 2)) +
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((dc->pc + 3) & ~3));
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/* no ext L32R */
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tcg_gen_qemu_ld32u(cpu_R[RRR_T], tmp, 0);
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tcg_temp_free(tmp);
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}
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break;
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case 2: /*LSAI*/
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break;
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case 3: /*LSCIp*/
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HAS_OPTION(XTENSA_OPTION_COPROCESSOR);
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break;
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case 4: /*MAC16d*/
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HAS_OPTION(XTENSA_OPTION_MAC16);
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break;
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case 5: /*CALLN*/
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switch (CALL_N) {
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case 0: /*CALL0*/
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tcg_gen_movi_i32(cpu_R[0], dc->next_pc);
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gen_jumpi(dc, (dc->pc & ~3) + (CALL_OFFSET_SE << 2) + 4, 0);
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break;
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case 1: /*CALL4w*/
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case 2: /*CALL8w*/
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case 3: /*CALL12w*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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break;
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}
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break;
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case 6: /*SI*/
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switch (CALL_N) {
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case 0: /*J*/
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gen_jumpi(dc, dc->pc + 4 + CALL_OFFSET_SE, 0);
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break;
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case 1: /*BZ*/
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{
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static const TCGCond cond[] = {
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TCG_COND_EQ, /*BEQZ*/
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TCG_COND_NE, /*BNEZ*/
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TCG_COND_LT, /*BLTZ*/
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TCG_COND_GE, /*BGEZ*/
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};
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gen_brcondi(dc, cond[BRI12_M & 3], cpu_R[BRI12_S], 0,
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4 + BRI12_IMM12_SE);
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}
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break;
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case 2: /*BI0*/
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{
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static const TCGCond cond[] = {
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TCG_COND_EQ, /*BEQI*/
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TCG_COND_NE, /*BNEI*/
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TCG_COND_LT, /*BLTI*/
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TCG_COND_GE, /*BGEI*/
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};
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gen_brcondi(dc, cond[BRI8_M & 3],
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cpu_R[BRI8_S], B4CONST[BRI8_R], 4 + BRI8_IMM8_SE);
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}
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break;
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case 3: /*BI1*/
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switch (BRI8_M) {
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case 0: /*ENTRYw*/
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HAS_OPTION(XTENSA_OPTION_WINDOWED_REGISTER);
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break;
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case 1: /*B1*/
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switch (BRI8_R) {
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case 0: /*BFp*/
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HAS_OPTION(XTENSA_OPTION_BOOLEAN);
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break;
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case 1: /*BTp*/
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HAS_OPTION(XTENSA_OPTION_BOOLEAN);
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break;
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case 8: /*LOOP*/
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break;
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case 9: /*LOOPNEZ*/
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break;
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case 10: /*LOOPGTZ*/
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break;
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default: /*reserved*/
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break;
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}
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break;
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case 2: /*BLTUI*/
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case 3: /*BGEUI*/
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gen_brcondi(dc, BRI8_M == 2 ? TCG_COND_LTU : TCG_COND_GEU,
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cpu_R[BRI8_S], B4CONSTU[BRI8_R], 4 + BRI8_IMM8_SE);
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break;
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}
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break;
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}
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break;
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case 7: /*B*/
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{
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TCGCond eq_ne = (RRI8_R & 8) ? TCG_COND_NE : TCG_COND_EQ;
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switch (RRI8_R & 7) {
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case 0: /*BNONE*/ /*BANY*/
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
|
|
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
case 1: /*BEQ*/ /*BNE*/
|
|
case 2: /*BLT*/ /*BGE*/
|
|
case 3: /*BLTU*/ /*BGEU*/
|
|
{
|
|
static const TCGCond cond[] = {
|
|
[1] = TCG_COND_EQ,
|
|
[2] = TCG_COND_LT,
|
|
[3] = TCG_COND_LTU,
|
|
[9] = TCG_COND_NE,
|
|
[10] = TCG_COND_GE,
|
|
[11] = TCG_COND_GEU,
|
|
};
|
|
gen_brcond(dc, cond[RRI8_R], cpu_R[RRI8_S], cpu_R[RRI8_T],
|
|
4 + RRI8_IMM8_SE);
|
|
}
|
|
break;
|
|
|
|
case 4: /*BALL*/ /*BNALL*/
|
|
{
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], cpu_R[RRI8_T]);
|
|
gen_brcond(dc, eq_ne, tmp, cpu_R[RRI8_T],
|
|
4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
case 5: /*BBC*/ /*BBS*/
|
|
{
|
|
TCGv_i32 bit = tcg_const_i32(1);
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_andi_i32(tmp, cpu_R[RRI8_T], 0x1f);
|
|
tcg_gen_shl_i32(bit, bit, tmp);
|
|
tcg_gen_and_i32(tmp, cpu_R[RRI8_S], bit);
|
|
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
tcg_temp_free(bit);
|
|
}
|
|
break;
|
|
|
|
case 6: /*BBCI*/ /*BBSI*/
|
|
case 7:
|
|
{
|
|
TCGv_i32 tmp = tcg_temp_new_i32();
|
|
tcg_gen_andi_i32(tmp, cpu_R[RRI8_S],
|
|
1 << (((RRI8_R & 1) << 4) | RRI8_T));
|
|
gen_brcondi(dc, eq_ne, tmp, 0, 4 + RRI8_IMM8_SE);
|
|
tcg_temp_free(tmp);
|
|
}
|
|
break;
|
|
|
|
}
|
|
}
|
|
break;
|
|
|
|
#define gen_narrow_load_store(type) do { \
|
|
TCGv_i32 addr = tcg_temp_new_i32(); \
|
|
tcg_gen_addi_i32(addr, cpu_R[RRRN_S], RRRN_R << 2); \
|
|
tcg_gen_qemu_##type(cpu_R[RRRN_T], addr, 0); \
|
|
tcg_temp_free(addr); \
|
|
} while (0)
|
|
|
|
case 8: /*L32I.Nn*/
|
|
gen_narrow_load_store(ld32u);
|
|
break;
|
|
|
|
case 9: /*S32I.Nn*/
|
|
gen_narrow_load_store(st32);
|
|
break;
|
|
#undef gen_narrow_load_store
|
|
|
|
case 10: /*ADD.Nn*/
|
|
tcg_gen_add_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], cpu_R[RRRN_T]);
|
|
break;
|
|
|
|
case 11: /*ADDI.Nn*/
|
|
tcg_gen_addi_i32(cpu_R[RRRN_R], cpu_R[RRRN_S], RRRN_T ? RRRN_T : -1);
|
|
break;
|
|
|
|
case 12: /*ST2n*/
|
|
if (RRRN_T < 8) { /*MOVI.Nn*/
|
|
tcg_gen_movi_i32(cpu_R[RRRN_S],
|
|
RRRN_R | (RRRN_T << 4) |
|
|
((RRRN_T & 6) == 6 ? 0xffffff80 : 0));
|
|
} else { /*BEQZ.Nn*/ /*BNEZ.Nn*/
|
|
TCGCond eq_ne = (RRRN_T & 4) ? TCG_COND_NE : TCG_COND_EQ;
|
|
|
|
gen_brcondi(dc, eq_ne, cpu_R[RRRN_S], 0,
|
|
4 + (RRRN_R | ((RRRN_T & 3) << 4)));
|
|
}
|
|
break;
|
|
|
|
case 13: /*ST3n*/
|
|
switch (RRRN_R) {
|
|
case 0: /*MOV.Nn*/
|
|
tcg_gen_mov_i32(cpu_R[RRRN_T], cpu_R[RRRN_S]);
|
|
break;
|
|
|
|
case 15: /*S3*/
|
|
switch (RRRN_T) {
|
|
case 0: /*RET.Nn*/
|
|
gen_jump(dc, cpu_R[0]);
|
|
break;
|
|
|
|
case 1: /*RETW.Nn*/
|
|
break;
|
|
|
|
case 2: /*BREAK.Nn*/
|
|
break;
|
|
|
|
case 3: /*NOP.Nn*/
|
|
break;
|
|
|
|
case 6: /*ILL.Nn*/
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
break;
|
|
|
|
default: /*reserved*/
|
|
break;
|
|
}
|
|
|
|
dc->pc = dc->next_pc;
|
|
return;
|
|
|
|
invalid_opcode:
|
|
qemu_log("INVALID(pc = %08x)\n", dc->pc);
|
|
dc->pc = dc->next_pc;
|
|
#undef HAS_OPTION
|
|
}
|
|
|
|
static void check_breakpoint(CPUState *env, DisasContext *dc)
|
|
{
|
|
CPUBreakpoint *bp;
|
|
|
|
if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
|
|
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
|
if (bp->pc == dc->pc) {
|
|
tcg_gen_movi_i32(cpu_pc, dc->pc);
|
|
gen_exception(EXCP_DEBUG);
|
|
dc->is_jmp = DISAS_UPDATE;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
static void gen_intermediate_code_internal(
|
|
CPUState *env, TranslationBlock *tb, int search_pc)
|
|
{
|
|
DisasContext dc;
|
|
int insn_count = 0;
|
|
int j, lj = -1;
|
|
uint16_t *gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
|
|
int max_insns = tb->cflags & CF_COUNT_MASK;
|
|
uint32_t pc_start = tb->pc;
|
|
uint32_t next_page_start =
|
|
(pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
|
|
|
|
if (max_insns == 0) {
|
|
max_insns = CF_COUNT_MASK;
|
|
}
|
|
|
|
dc.config = env->config;
|
|
dc.singlestep_enabled = env->singlestep_enabled;
|
|
dc.tb = tb;
|
|
dc.pc = pc_start;
|
|
dc.is_jmp = DISAS_NEXT;
|
|
|
|
gen_icount_start();
|
|
|
|
do {
|
|
check_breakpoint(env, &dc);
|
|
|
|
if (search_pc) {
|
|
j = gen_opc_ptr - gen_opc_buf;
|
|
if (lj < j) {
|
|
lj++;
|
|
while (lj < j) {
|
|
gen_opc_instr_start[lj++] = 0;
|
|
}
|
|
}
|
|
gen_opc_pc[lj] = dc.pc;
|
|
gen_opc_instr_start[lj] = 1;
|
|
gen_opc_icount[lj] = insn_count;
|
|
}
|
|
|
|
if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP))) {
|
|
tcg_gen_debug_insn_start(dc.pc);
|
|
}
|
|
|
|
disas_xtensa_insn(&dc);
|
|
++insn_count;
|
|
if (env->singlestep_enabled) {
|
|
tcg_gen_movi_i32(cpu_pc, dc.pc);
|
|
gen_exception(EXCP_DEBUG);
|
|
break;
|
|
}
|
|
} while (dc.is_jmp == DISAS_NEXT &&
|
|
insn_count < max_insns &&
|
|
dc.pc < next_page_start &&
|
|
gen_opc_ptr < gen_opc_end);
|
|
|
|
if (dc.is_jmp == DISAS_NEXT) {
|
|
gen_jumpi(&dc, dc.pc, 0);
|
|
}
|
|
gen_icount_end(tb, insn_count);
|
|
*gen_opc_ptr = INDEX_op_end;
|
|
|
|
if (!search_pc) {
|
|
tb->size = dc.pc - pc_start;
|
|
tb->icount = insn_count;
|
|
}
|
|
}
|
|
|
|
void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(env, tb, 0);
|
|
}
|
|
|
|
void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
|
{
|
|
gen_intermediate_code_internal(env, tb, 1);
|
|
}
|
|
|
|
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
|
int flags)
|
|
{
|
|
int i;
|
|
|
|
cpu_fprintf(f, "PC=%08x\n", env->pc);
|
|
|
|
for (i = 0; i < 16; ++i) {
|
|
cpu_fprintf(f, "A%02d=%08x%c", i, env->regs[i],
|
|
(i % 4) == 3 ? '\n' : ' ');
|
|
}
|
|
}
|
|
|
|
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
|
|
{
|
|
env->pc = gen_opc_pc[pc_pos];
|
|
}
|