bdbb9d6999
This is all that is required by tcg/ from exec-all.h. Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
150 lines
5.6 KiB
C
150 lines
5.6 KiB
C
/* SPDX-License-Identifier: LGPL-2.1-or-later */
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/*
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* Definition of TranslationBlock.
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* Copyright (c) 2003 Fabrice Bellard
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*/
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#ifndef EXEC_TRANSLATION_BLOCK_H
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#define EXEC_TRANSLATION_BLOCK_H
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#include "qemu/atomic.h"
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#include "qemu/thread.h"
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#include "qemu/interval-tree.h"
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#include "exec/cpu-common.h"
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#include "exec/target_page.h"
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/*
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* Page tracking code uses ram addresses in system mode, and virtual
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* addresses in userspace mode. Define tb_page_addr_t to be an
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* appropriate type.
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*/
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#if defined(CONFIG_USER_ONLY)
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typedef vaddr tb_page_addr_t;
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#define TB_PAGE_ADDR_FMT "%" VADDR_PRIx
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#else
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typedef ram_addr_t tb_page_addr_t;
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#define TB_PAGE_ADDR_FMT RAM_ADDR_FMT
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#endif
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/*
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* Translation Cache-related fields of a TB.
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* This struct exists just for convenience; we keep track of TB's in a binary
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* search tree, and the only fields needed to compare TB's in the tree are
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* @ptr and @size.
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* Note: the address of search data can be obtained by adding @size to @ptr.
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*/
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struct tb_tc {
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const void *ptr; /* pointer to the translated code */
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size_t size;
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};
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struct TranslationBlock {
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/*
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* Guest PC corresponding to this block. This must be the true
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* virtual address. Therefore e.g. x86 stores EIP + CS_BASE, and
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* targets like Arm, MIPS, HP-PA, which reuse low bits for ISA or
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* privilege, must store those bits elsewhere.
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*
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* If CF_PCREL, the opcodes for the TranslationBlock are written
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* such that the TB is associated only with the physical page and
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* may be run in any virtual address context. In this case, PC
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* must always be taken from ENV in a target-specific manner.
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* Unwind information is taken as offsets from the page, to be
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* deposited into the "current" PC.
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*/
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vaddr pc;
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/*
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* Target-specific data associated with the TranslationBlock, e.g.:
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* x86: the original user, the Code Segment virtual base,
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* arm: an extension of tb->flags,
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* s390x: instruction data for EXECUTE,
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* sparc: the next pc of the instruction queue (for delay slots).
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*/
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uint64_t cs_base;
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uint32_t flags; /* flags defining in which context the code was generated */
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uint32_t cflags; /* compile flags */
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/* Note that TCG_MAX_INSNS is 512; we validate this match elsewhere. */
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#define CF_COUNT_MASK 0x000001ff
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#define CF_NO_GOTO_TB 0x00000200 /* Do not chain with goto_tb */
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#define CF_NO_GOTO_PTR 0x00000400 /* Do not chain with goto_ptr */
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#define CF_SINGLE_STEP 0x00000800 /* gdbstub single-step in effect */
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#define CF_LAST_IO 0x00008000 /* Last insn may be an IO access. */
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#define CF_MEMI_ONLY 0x00010000 /* Only instrument memory ops */
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#define CF_USE_ICOUNT 0x00020000
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#define CF_INVALID 0x00040000 /* TB is stale. Set with @jmp_lock held */
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#define CF_PARALLEL 0x00080000 /* Generate code for a parallel context */
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#define CF_NOIRQ 0x00100000 /* Generate an uninterruptible TB */
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#define CF_PCREL 0x00200000 /* Opcodes in TB are PC-relative */
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#define CF_CLUSTER_MASK 0xff000000 /* Top 8 bits are cluster ID */
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#define CF_CLUSTER_SHIFT 24
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/*
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* Above fields used for comparing
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*/
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/* size of target code for this block (1 <= size <= TARGET_PAGE_SIZE) */
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uint16_t size;
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uint16_t icount;
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struct tb_tc tc;
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/*
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* Track tb_page_addr_t intervals that intersect this TB.
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* For user-only, the virtual addresses are always contiguous,
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* and we use a unified interval tree. For system, we use a
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* linked list headed in each PageDesc. Within the list, the lsb
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* of the previous pointer tells the index of page_next[], and the
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* list is protected by the PageDesc lock(s).
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*/
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#ifdef CONFIG_USER_ONLY
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IntervalTreeNode itree;
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#else
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uintptr_t page_next[2];
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tb_page_addr_t page_addr[2];
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#endif
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/* jmp_lock placed here to fill a 4-byte hole. Its documentation is below */
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QemuSpin jmp_lock;
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/* The following data are used to directly call another TB from
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* the code of this one. This can be done either by emitting direct or
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* indirect native jump instructions. These jumps are reset so that the TB
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* just continues its execution. The TB can be linked to another one by
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* setting one of the jump targets (or patching the jump instruction). Only
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* two of such jumps are supported.
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*/
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#define TB_JMP_OFFSET_INVALID 0xffff /* indicates no jump generated */
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uint16_t jmp_reset_offset[2]; /* offset of original jump target */
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uint16_t jmp_insn_offset[2]; /* offset of direct jump insn */
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uintptr_t jmp_target_addr[2]; /* target address */
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/*
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* Each TB has a NULL-terminated list (jmp_list_head) of incoming jumps.
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* Each TB can have two outgoing jumps, and therefore can participate
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* in two lists. The list entries are kept in jmp_list_next[2]. The least
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* significant bit (LSB) of the pointers in these lists is used to encode
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* which of the two list entries is to be used in the pointed TB.
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*
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* List traversals are protected by jmp_lock. The destination TB of each
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* outgoing jump is kept in jmp_dest[] so that the appropriate jmp_lock
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* can be acquired from any origin TB.
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*
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* jmp_dest[] are tagged pointers as well. The LSB is set when the TB is
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* being invalidated, so that no further outgoing jumps from it can be set.
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*
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* jmp_lock also protects the CF_INVALID cflag; a jump must not be chained
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* to a destination TB that has CF_INVALID set.
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*/
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uintptr_t jmp_list_head;
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uintptr_t jmp_list_next[2];
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uintptr_t jmp_dest[2];
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};
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/* The alignment given to TranslationBlock during allocation. */
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#define CODE_GEN_ALIGN 16
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#endif /* EXEC_TRANSLATION_BLOCK_H */
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