qemu-e2k/target
Kurban Mallachiev be1b21e885 target-ppc: Don't invalidate non-supported msr bits
The msr invalidation code (commits 993eb and 2360b) inverts all
bits except MSR_TGPR and MSR_HVB. On non PowerPC 601 processors
this leads to incorrect change of excp_prefix in hreg_store_msr()
function. The problem is that new msr value get multiplied by msr_mask
and inverted msr does not, thus values of MSR_EP bit in new msr value
and inverted msr are distinct, so that excp_prefix changes but should
not.

Signed-off-by: Kurban Mallachiev <mallachiev@ispras.ru>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2017-11-30 14:56:42 +11:00
..
alpha x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
arm arm: check regime, not current state, for ATS write PAR format 2017-11-20 13:42:25 +00:00
cris x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
hppa Capstone disassembler 2017-10-27 08:04:51 +01:00
i386 Miscellaneous bugfixes 2017-11-16 14:42:54 +00:00
lm32 x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
m68k x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
microblaze Capstone disassembler 2017-10-27 08:04:51 +01:00
mips x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
moxie moxie: cleanup cpu type name composition 2017-10-27 16:03:54 +02:00
nios2 Capstone disassembler 2017-10-27 08:04:51 +01:00
openrisc x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
ppc target-ppc: Don't invalidate non-supported msr bits 2017-11-30 14:56:42 +11:00
s390x s390x/tcg: fix DIAG 308 with > 1 VCPU (MTTCG) 2017-11-20 09:31:46 +01:00
sh4 x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
sparc linux-user/sparc: Put address for data faults where linux-user expects it 2017-11-07 21:59:18 +02:00
tilegx tcg: Initialize cpu_env generically 2017-10-24 13:53:42 -07:00
tricore x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
unicore32 x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00
xtensa x86/cpu/numa queue, 2017-10-27 2017-10-30 10:11:22 +00:00