c0198c5f87
In preparation for removing assumptions about XSAVE area offsets, pass a buffer pointer and buffer length to the XSAVE helper functions. Signed-off-by: David Edmondson <david.edmondson@oracle.com> Message-Id: <20210705104632.2902400-5-david.edmondson@oracle.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
464 lines
16 KiB
C
464 lines
16 KiB
C
/*
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* Copyright (c) 2003-2008 Fabrice Bellard
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* Copyright (C) 2016 Veertu Inc,
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* Copyright (C) 2017 Google Inc,
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2.1 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "qemu/osdep.h"
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#include "qemu-common.h"
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#include "x86hvf.h"
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#include "vmx.h"
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#include "vmcs.h"
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#include "cpu.h"
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#include "x86_descr.h"
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#include "x86_decode.h"
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#include "sysemu/hw_accel.h"
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#include "hw/i386/apic_internal.h"
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#include <Hypervisor/hv.h>
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#include <Hypervisor/hv_vmx.h>
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void hvf_set_segment(struct CPUState *cpu, struct vmx_segment *vmx_seg,
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SegmentCache *qseg, bool is_tr)
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{
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vmx_seg->sel = qseg->selector;
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vmx_seg->base = qseg->base;
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vmx_seg->limit = qseg->limit;
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if (!qseg->selector && !x86_is_real(cpu) && !is_tr) {
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/* the TR register is usable after processor reset despite
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* having a null selector */
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vmx_seg->ar = 1 << 16;
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return;
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}
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vmx_seg->ar = (qseg->flags >> DESC_TYPE_SHIFT) & 0xf;
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vmx_seg->ar |= ((qseg->flags >> DESC_G_SHIFT) & 1) << 15;
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vmx_seg->ar |= ((qseg->flags >> DESC_B_SHIFT) & 1) << 14;
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vmx_seg->ar |= ((qseg->flags >> DESC_L_SHIFT) & 1) << 13;
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vmx_seg->ar |= ((qseg->flags >> DESC_AVL_SHIFT) & 1) << 12;
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vmx_seg->ar |= ((qseg->flags >> DESC_P_SHIFT) & 1) << 7;
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vmx_seg->ar |= ((qseg->flags >> DESC_DPL_SHIFT) & 3) << 5;
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vmx_seg->ar |= ((qseg->flags >> DESC_S_SHIFT) & 1) << 4;
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}
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void hvf_get_segment(SegmentCache *qseg, struct vmx_segment *vmx_seg)
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{
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qseg->limit = vmx_seg->limit;
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qseg->base = vmx_seg->base;
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qseg->selector = vmx_seg->sel;
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qseg->flags = ((vmx_seg->ar & 0xf) << DESC_TYPE_SHIFT) |
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(((vmx_seg->ar >> 4) & 1) << DESC_S_SHIFT) |
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(((vmx_seg->ar >> 5) & 3) << DESC_DPL_SHIFT) |
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(((vmx_seg->ar >> 7) & 1) << DESC_P_SHIFT) |
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(((vmx_seg->ar >> 12) & 1) << DESC_AVL_SHIFT) |
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(((vmx_seg->ar >> 13) & 1) << DESC_L_SHIFT) |
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(((vmx_seg->ar >> 14) & 1) << DESC_B_SHIFT) |
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(((vmx_seg->ar >> 15) & 1) << DESC_G_SHIFT);
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}
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void hvf_put_xsave(CPUState *cpu_state)
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{
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void *xsave = X86_CPU(cpu_state)->env.xsave_buf;
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uint32_t xsave_len = X86_CPU(cpu_state)->env.xsave_buf_len;
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x86_cpu_xsave_all_areas(X86_CPU(cpu_state), xsave, xsave_len);
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if (hv_vcpu_write_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) {
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abort();
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}
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}
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void hvf_put_segments(CPUState *cpu_state)
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{
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CPUX86State *env = &X86_CPU(cpu_state)->env;
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struct vmx_segment seg;
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wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT, env->idt.limit);
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wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE, env->idt.base);
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wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT, env->gdt.limit);
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wvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE, env->gdt.base);
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/* wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR2, env->cr[2]); */
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wvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3, env->cr[3]);
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vmx_update_tpr(cpu_state);
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wvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER, env->efer);
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macvm_set_cr4(cpu_state->hvf->fd, env->cr[4]);
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macvm_set_cr0(cpu_state->hvf->fd, env->cr[0]);
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hvf_set_segment(cpu_state, &seg, &env->segs[R_CS], false);
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vmx_write_segment_descriptor(cpu_state, &seg, R_CS);
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hvf_set_segment(cpu_state, &seg, &env->segs[R_DS], false);
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vmx_write_segment_descriptor(cpu_state, &seg, R_DS);
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hvf_set_segment(cpu_state, &seg, &env->segs[R_ES], false);
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vmx_write_segment_descriptor(cpu_state, &seg, R_ES);
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hvf_set_segment(cpu_state, &seg, &env->segs[R_SS], false);
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vmx_write_segment_descriptor(cpu_state, &seg, R_SS);
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hvf_set_segment(cpu_state, &seg, &env->segs[R_FS], false);
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vmx_write_segment_descriptor(cpu_state, &seg, R_FS);
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hvf_set_segment(cpu_state, &seg, &env->segs[R_GS], false);
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vmx_write_segment_descriptor(cpu_state, &seg, R_GS);
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hvf_set_segment(cpu_state, &seg, &env->tr, true);
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vmx_write_segment_descriptor(cpu_state, &seg, R_TR);
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hvf_set_segment(cpu_state, &seg, &env->ldt, false);
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vmx_write_segment_descriptor(cpu_state, &seg, R_LDTR);
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hv_vcpu_flush(cpu_state->hvf->fd);
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}
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void hvf_put_msrs(CPUState *cpu_state)
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{
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CPUX86State *env = &X86_CPU(cpu_state)->env;
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS,
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env->sysenter_cs);
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP,
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env->sysenter_esp);
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP,
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env->sysenter_eip);
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_STAR, env->star);
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#ifdef TARGET_X86_64
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_CSTAR, env->cstar);
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, env->kernelgsbase);
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FMASK, env->fmask);
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_LSTAR, env->lstar);
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#endif
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_GSBASE, env->segs[R_GS].base);
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hv_vcpu_write_msr(cpu_state->hvf->fd, MSR_FSBASE, env->segs[R_FS].base);
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}
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void hvf_get_xsave(CPUState *cpu_state)
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{
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void *xsave = X86_CPU(cpu_state)->env.xsave_buf;
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uint32_t xsave_len = X86_CPU(cpu_state)->env.xsave_buf_len;
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if (hv_vcpu_read_fpstate(cpu_state->hvf->fd, xsave, xsave_len)) {
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abort();
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}
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x86_cpu_xrstor_all_areas(X86_CPU(cpu_state), xsave, xsave_len);
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}
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void hvf_get_segments(CPUState *cpu_state)
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{
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CPUX86State *env = &X86_CPU(cpu_state)->env;
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struct vmx_segment seg;
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env->interrupt_injected = -1;
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vmx_read_segment_descriptor(cpu_state, &seg, R_CS);
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hvf_get_segment(&env->segs[R_CS], &seg);
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vmx_read_segment_descriptor(cpu_state, &seg, R_DS);
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hvf_get_segment(&env->segs[R_DS], &seg);
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vmx_read_segment_descriptor(cpu_state, &seg, R_ES);
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hvf_get_segment(&env->segs[R_ES], &seg);
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vmx_read_segment_descriptor(cpu_state, &seg, R_FS);
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hvf_get_segment(&env->segs[R_FS], &seg);
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vmx_read_segment_descriptor(cpu_state, &seg, R_GS);
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hvf_get_segment(&env->segs[R_GS], &seg);
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vmx_read_segment_descriptor(cpu_state, &seg, R_SS);
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hvf_get_segment(&env->segs[R_SS], &seg);
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vmx_read_segment_descriptor(cpu_state, &seg, R_TR);
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hvf_get_segment(&env->tr, &seg);
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vmx_read_segment_descriptor(cpu_state, &seg, R_LDTR);
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hvf_get_segment(&env->ldt, &seg);
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env->idt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_LIMIT);
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env->idt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IDTR_BASE);
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env->gdt.limit = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_LIMIT);
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env->gdt.base = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_GDTR_BASE);
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env->cr[0] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR0);
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env->cr[2] = 0;
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env->cr[3] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR3);
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env->cr[4] = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_CR4);
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env->efer = rvmcs(cpu_state->hvf->fd, VMCS_GUEST_IA32_EFER);
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}
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void hvf_get_msrs(CPUState *cpu_state)
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{
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CPUX86State *env = &X86_CPU(cpu_state)->env;
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uint64_t tmp;
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_CS, &tmp);
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env->sysenter_cs = tmp;
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_ESP, &tmp);
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env->sysenter_esp = tmp;
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_SYSENTER_EIP, &tmp);
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env->sysenter_eip = tmp;
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_STAR, &env->star);
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#ifdef TARGET_X86_64
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_CSTAR, &env->cstar);
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_KERNELGSBASE, &env->kernelgsbase);
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_FMASK, &env->fmask);
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_LSTAR, &env->lstar);
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#endif
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hv_vcpu_read_msr(cpu_state->hvf->fd, MSR_IA32_APICBASE, &tmp);
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env->tsc = rdtscp() + rvmcs(cpu_state->hvf->fd, VMCS_TSC_OFFSET);
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}
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int hvf_put_registers(CPUState *cpu_state)
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{
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X86CPU *x86cpu = X86_CPU(cpu_state);
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CPUX86State *env = &x86cpu->env;
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wreg(cpu_state->hvf->fd, HV_X86_RAX, env->regs[R_EAX]);
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wreg(cpu_state->hvf->fd, HV_X86_RBX, env->regs[R_EBX]);
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wreg(cpu_state->hvf->fd, HV_X86_RCX, env->regs[R_ECX]);
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wreg(cpu_state->hvf->fd, HV_X86_RDX, env->regs[R_EDX]);
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wreg(cpu_state->hvf->fd, HV_X86_RBP, env->regs[R_EBP]);
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wreg(cpu_state->hvf->fd, HV_X86_RSP, env->regs[R_ESP]);
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wreg(cpu_state->hvf->fd, HV_X86_RSI, env->regs[R_ESI]);
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wreg(cpu_state->hvf->fd, HV_X86_RDI, env->regs[R_EDI]);
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wreg(cpu_state->hvf->fd, HV_X86_R8, env->regs[8]);
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wreg(cpu_state->hvf->fd, HV_X86_R9, env->regs[9]);
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wreg(cpu_state->hvf->fd, HV_X86_R10, env->regs[10]);
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wreg(cpu_state->hvf->fd, HV_X86_R11, env->regs[11]);
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wreg(cpu_state->hvf->fd, HV_X86_R12, env->regs[12]);
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wreg(cpu_state->hvf->fd, HV_X86_R13, env->regs[13]);
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wreg(cpu_state->hvf->fd, HV_X86_R14, env->regs[14]);
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wreg(cpu_state->hvf->fd, HV_X86_R15, env->regs[15]);
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wreg(cpu_state->hvf->fd, HV_X86_RFLAGS, env->eflags);
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wreg(cpu_state->hvf->fd, HV_X86_RIP, env->eip);
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wreg(cpu_state->hvf->fd, HV_X86_XCR0, env->xcr0);
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hvf_put_xsave(cpu_state);
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hvf_put_segments(cpu_state);
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hvf_put_msrs(cpu_state);
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wreg(cpu_state->hvf->fd, HV_X86_DR0, env->dr[0]);
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wreg(cpu_state->hvf->fd, HV_X86_DR1, env->dr[1]);
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wreg(cpu_state->hvf->fd, HV_X86_DR2, env->dr[2]);
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wreg(cpu_state->hvf->fd, HV_X86_DR3, env->dr[3]);
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wreg(cpu_state->hvf->fd, HV_X86_DR4, env->dr[4]);
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wreg(cpu_state->hvf->fd, HV_X86_DR5, env->dr[5]);
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wreg(cpu_state->hvf->fd, HV_X86_DR6, env->dr[6]);
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wreg(cpu_state->hvf->fd, HV_X86_DR7, env->dr[7]);
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return 0;
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}
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int hvf_get_registers(CPUState *cpu_state)
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{
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X86CPU *x86cpu = X86_CPU(cpu_state);
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CPUX86State *env = &x86cpu->env;
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env->regs[R_EAX] = rreg(cpu_state->hvf->fd, HV_X86_RAX);
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env->regs[R_EBX] = rreg(cpu_state->hvf->fd, HV_X86_RBX);
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env->regs[R_ECX] = rreg(cpu_state->hvf->fd, HV_X86_RCX);
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env->regs[R_EDX] = rreg(cpu_state->hvf->fd, HV_X86_RDX);
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env->regs[R_EBP] = rreg(cpu_state->hvf->fd, HV_X86_RBP);
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env->regs[R_ESP] = rreg(cpu_state->hvf->fd, HV_X86_RSP);
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env->regs[R_ESI] = rreg(cpu_state->hvf->fd, HV_X86_RSI);
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env->regs[R_EDI] = rreg(cpu_state->hvf->fd, HV_X86_RDI);
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env->regs[8] = rreg(cpu_state->hvf->fd, HV_X86_R8);
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env->regs[9] = rreg(cpu_state->hvf->fd, HV_X86_R9);
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env->regs[10] = rreg(cpu_state->hvf->fd, HV_X86_R10);
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env->regs[11] = rreg(cpu_state->hvf->fd, HV_X86_R11);
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env->regs[12] = rreg(cpu_state->hvf->fd, HV_X86_R12);
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env->regs[13] = rreg(cpu_state->hvf->fd, HV_X86_R13);
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env->regs[14] = rreg(cpu_state->hvf->fd, HV_X86_R14);
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env->regs[15] = rreg(cpu_state->hvf->fd, HV_X86_R15);
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env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS);
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env->eip = rreg(cpu_state->hvf->fd, HV_X86_RIP);
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hvf_get_xsave(cpu_state);
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env->xcr0 = rreg(cpu_state->hvf->fd, HV_X86_XCR0);
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hvf_get_segments(cpu_state);
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hvf_get_msrs(cpu_state);
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env->dr[0] = rreg(cpu_state->hvf->fd, HV_X86_DR0);
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env->dr[1] = rreg(cpu_state->hvf->fd, HV_X86_DR1);
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env->dr[2] = rreg(cpu_state->hvf->fd, HV_X86_DR2);
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env->dr[3] = rreg(cpu_state->hvf->fd, HV_X86_DR3);
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env->dr[4] = rreg(cpu_state->hvf->fd, HV_X86_DR4);
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env->dr[5] = rreg(cpu_state->hvf->fd, HV_X86_DR5);
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env->dr[6] = rreg(cpu_state->hvf->fd, HV_X86_DR6);
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env->dr[7] = rreg(cpu_state->hvf->fd, HV_X86_DR7);
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x86_update_hflags(env);
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return 0;
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}
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static void vmx_set_int_window_exiting(CPUState *cpu)
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{
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uint64_t val;
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val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
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wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val |
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VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
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}
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void vmx_clear_int_window_exiting(CPUState *cpu)
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{
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uint64_t val;
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val = rvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS);
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wvmcs(cpu->hvf->fd, VMCS_PRI_PROC_BASED_CTLS, val &
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~VMCS_PRI_PROC_BASED_CTLS_INT_WINDOW_EXITING);
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}
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bool hvf_inject_interrupts(CPUState *cpu_state)
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{
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X86CPU *x86cpu = X86_CPU(cpu_state);
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CPUX86State *env = &x86cpu->env;
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uint8_t vector;
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uint64_t intr_type;
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bool have_event = true;
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if (env->interrupt_injected != -1) {
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vector = env->interrupt_injected;
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if (env->ins_len) {
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intr_type = VMCS_INTR_T_SWINTR;
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} else {
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intr_type = VMCS_INTR_T_HWINTR;
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}
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} else if (env->exception_nr != -1) {
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vector = env->exception_nr;
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if (vector == EXCP03_INT3 || vector == EXCP04_INTO) {
|
|
intr_type = VMCS_INTR_T_SWEXCEPTION;
|
|
} else {
|
|
intr_type = VMCS_INTR_T_HWEXCEPTION;
|
|
}
|
|
} else if (env->nmi_injected) {
|
|
vector = EXCP02_NMI;
|
|
intr_type = VMCS_INTR_T_NMI;
|
|
} else {
|
|
have_event = false;
|
|
}
|
|
|
|
uint64_t info = 0;
|
|
if (have_event) {
|
|
info = vector | intr_type | VMCS_INTR_VALID;
|
|
uint64_t reason = rvmcs(cpu_state->hvf->fd, VMCS_EXIT_REASON);
|
|
if (env->nmi_injected && reason != EXIT_REASON_TASK_SWITCH) {
|
|
vmx_clear_nmi_blocking(cpu_state);
|
|
}
|
|
|
|
if (!(env->hflags2 & HF2_NMI_MASK) || intr_type != VMCS_INTR_T_NMI) {
|
|
info &= ~(1 << 12); /* clear undefined bit */
|
|
if (intr_type == VMCS_INTR_T_SWINTR ||
|
|
intr_type == VMCS_INTR_T_SWEXCEPTION) {
|
|
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INST_LENGTH, env->ins_len);
|
|
}
|
|
|
|
if (env->has_error_code) {
|
|
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_EXCEPTION_ERROR,
|
|
env->error_code);
|
|
/* Indicate that VMCS_ENTRY_EXCEPTION_ERROR is valid */
|
|
info |= VMCS_INTR_DEL_ERRCODE;
|
|
}
|
|
/*printf("reinject %lx err %d\n", info, err);*/
|
|
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info);
|
|
};
|
|
}
|
|
|
|
if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) {
|
|
if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) {
|
|
cpu_state->interrupt_request &= ~CPU_INTERRUPT_NMI;
|
|
info = VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI;
|
|
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, info);
|
|
} else {
|
|
vmx_set_nmi_window_exiting(cpu_state);
|
|
}
|
|
}
|
|
|
|
if (!(env->hflags & HF_INHIBIT_IRQ_MASK) &&
|
|
(cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
(env->eflags & IF_MASK) && !(info & VMCS_INTR_VALID)) {
|
|
int line = cpu_get_pic_interrupt(&x86cpu->env);
|
|
cpu_state->interrupt_request &= ~CPU_INTERRUPT_HARD;
|
|
if (line >= 0) {
|
|
wvmcs(cpu_state->hvf->fd, VMCS_ENTRY_INTR_INFO, line |
|
|
VMCS_INTR_VALID | VMCS_INTR_T_HWINTR);
|
|
}
|
|
}
|
|
if (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) {
|
|
vmx_set_int_window_exiting(cpu_state);
|
|
}
|
|
return (cpu_state->interrupt_request
|
|
& (CPU_INTERRUPT_INIT | CPU_INTERRUPT_TPR));
|
|
}
|
|
|
|
int hvf_process_events(CPUState *cpu_state)
|
|
{
|
|
X86CPU *cpu = X86_CPU(cpu_state);
|
|
CPUX86State *env = &cpu->env;
|
|
|
|
if (!cpu_state->vcpu_dirty) {
|
|
/* light weight sync for CPU_INTERRUPT_HARD and IF_MASK */
|
|
env->eflags = rreg(cpu_state->hvf->fd, HV_X86_RFLAGS);
|
|
}
|
|
|
|
if (cpu_state->interrupt_request & CPU_INTERRUPT_INIT) {
|
|
cpu_synchronize_state(cpu_state);
|
|
do_cpu_init(cpu);
|
|
}
|
|
|
|
if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) {
|
|
cpu_state->interrupt_request &= ~CPU_INTERRUPT_POLL;
|
|
apic_poll_irq(cpu->apic_state);
|
|
}
|
|
if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) &&
|
|
(env->eflags & IF_MASK)) ||
|
|
(cpu_state->interrupt_request & CPU_INTERRUPT_NMI)) {
|
|
cpu_state->halted = 0;
|
|
}
|
|
if (cpu_state->interrupt_request & CPU_INTERRUPT_SIPI) {
|
|
cpu_synchronize_state(cpu_state);
|
|
do_cpu_sipi(cpu);
|
|
}
|
|
if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) {
|
|
cpu_state->interrupt_request &= ~CPU_INTERRUPT_TPR;
|
|
cpu_synchronize_state(cpu_state);
|
|
apic_handle_tpr_access_report(cpu->apic_state, env->eip,
|
|
env->tpr_access_type);
|
|
}
|
|
return cpu_state->halted;
|
|
}
|