Bastian Koppelmann 9371557115 target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA ... Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Richard Henderson <rth@twiddle.net>		2015-05-22 17:02:34 +02:00
..
cpu-qom.h	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
cpu.c	target-tricore: introduce ISA v1.6.1 feature	2015-05-22 17:02:33 +02:00
cpu.h	target-tricore: introduce ISA v1.6.1 feature	2015-05-22 17:02:33 +02:00
csfr.def	target-tricore: Fix new typos	2015-01-15 10:44:13 +03:00
helper.c	target-tricore: Remove the dummy interrupt boilerplate	2014-09-25 18:54:22 +01:00
helper.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00
Makefile.objs
op_helper.c	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00
translate.c	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00
tricore-defs.h
tricore-opcodes.h	target-tricore: add RR_DIV and RR_DIV_U instructions of the v1.6 ISA	2015-05-22 17:02:34 +02:00