503 lines
12 KiB
C++
503 lines
12 KiB
C++
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* Copyright (c) 2021 Loongson Technology Corporation Limited
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*
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* LoongArch translation routines for the privileged instructions.
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*/
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#include "cpu-csr.h"
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#ifdef CONFIG_USER_ONLY
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#define GEN_FALSE_TRANS(name) \
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static bool trans_##name(DisasContext *ctx, arg_##name * a) \
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{ \
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return false; \
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}
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GEN_FALSE_TRANS(csrrd)
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GEN_FALSE_TRANS(csrwr)
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GEN_FALSE_TRANS(csrxchg)
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GEN_FALSE_TRANS(iocsrrd_b)
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GEN_FALSE_TRANS(iocsrrd_h)
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GEN_FALSE_TRANS(iocsrrd_w)
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GEN_FALSE_TRANS(iocsrrd_d)
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GEN_FALSE_TRANS(iocsrwr_b)
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GEN_FALSE_TRANS(iocsrwr_h)
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GEN_FALSE_TRANS(iocsrwr_w)
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GEN_FALSE_TRANS(iocsrwr_d)
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GEN_FALSE_TRANS(tlbsrch)
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GEN_FALSE_TRANS(tlbrd)
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GEN_FALSE_TRANS(tlbwr)
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GEN_FALSE_TRANS(tlbfill)
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GEN_FALSE_TRANS(tlbclr)
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GEN_FALSE_TRANS(tlbflush)
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GEN_FALSE_TRANS(invtlb)
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GEN_FALSE_TRANS(cacop)
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GEN_FALSE_TRANS(ldpte)
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GEN_FALSE_TRANS(lddir)
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GEN_FALSE_TRANS(ertn)
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GEN_FALSE_TRANS(dbcl)
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GEN_FALSE_TRANS(idle)
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#else
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typedef void (*GenCSRRead)(TCGv dest, TCGv_ptr env);
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typedef void (*GenCSRWrite)(TCGv dest, TCGv_ptr env, TCGv src);
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typedef struct {
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int offset;
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int flags;
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GenCSRRead readfn;
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GenCSRWrite writefn;
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} CSRInfo;
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enum {
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CSRFL_READONLY = (1 << 0),
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CSRFL_EXITTB = (1 << 1),
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CSRFL_IO = (1 << 2),
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};
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#define CSR_OFF_FUNCS(NAME, FL, RD, WR) \
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[LOONGARCH_CSR_##NAME] = { \
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.offset = offsetof(CPULoongArchState, CSR_##NAME), \
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.flags = FL, .readfn = RD, .writefn = WR \
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}
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#define CSR_OFF_ARRAY(NAME, N) \
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[LOONGARCH_CSR_##NAME(N)] = { \
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.offset = offsetof(CPULoongArchState, CSR_##NAME[N]), \
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.flags = 0, .readfn = NULL, .writefn = NULL \
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}
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#define CSR_OFF_FLAGS(NAME, FL) \
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CSR_OFF_FUNCS(NAME, FL, NULL, NULL)
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#define CSR_OFF(NAME) \
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CSR_OFF_FLAGS(NAME, 0)
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static const CSRInfo csr_info[] = {
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CSR_OFF_FLAGS(CRMD, CSRFL_EXITTB),
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CSR_OFF(PRMD),
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CSR_OFF_FLAGS(EUEN, CSRFL_EXITTB),
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CSR_OFF_FLAGS(MISC, CSRFL_READONLY),
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CSR_OFF(ECFG),
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CSR_OFF_FUNCS(ESTAT, CSRFL_EXITTB, NULL, gen_helper_csrwr_estat),
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CSR_OFF(ERA),
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CSR_OFF(BADV),
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CSR_OFF_FLAGS(BADI, CSRFL_READONLY),
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CSR_OFF(EENTRY),
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CSR_OFF(TLBIDX),
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CSR_OFF(TLBEHI),
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CSR_OFF(TLBELO0),
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CSR_OFF(TLBELO1),
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CSR_OFF_FUNCS(ASID, CSRFL_EXITTB, NULL, gen_helper_csrwr_asid),
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CSR_OFF(PGDL),
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CSR_OFF(PGDH),
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CSR_OFF_FUNCS(PGD, CSRFL_READONLY, gen_helper_csrrd_pgd, NULL),
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CSR_OFF(PWCL),
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CSR_OFF(PWCH),
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CSR_OFF(STLBPS),
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CSR_OFF(RVACFG),
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[LOONGARCH_CSR_CPUID] = {
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.offset = (int)offsetof(CPUState, cpu_index)
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- (int)offsetof(LoongArchCPU, env),
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.flags = CSRFL_READONLY,
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.readfn = NULL,
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.writefn = NULL
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},
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CSR_OFF_FLAGS(PRCFG1, CSRFL_READONLY),
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CSR_OFF_FLAGS(PRCFG2, CSRFL_READONLY),
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CSR_OFF_FLAGS(PRCFG3, CSRFL_READONLY),
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CSR_OFF_ARRAY(SAVE, 0),
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CSR_OFF_ARRAY(SAVE, 1),
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CSR_OFF_ARRAY(SAVE, 2),
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CSR_OFF_ARRAY(SAVE, 3),
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CSR_OFF_ARRAY(SAVE, 4),
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CSR_OFF_ARRAY(SAVE, 5),
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CSR_OFF_ARRAY(SAVE, 6),
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CSR_OFF_ARRAY(SAVE, 7),
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CSR_OFF_ARRAY(SAVE, 8),
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CSR_OFF_ARRAY(SAVE, 9),
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CSR_OFF_ARRAY(SAVE, 10),
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CSR_OFF_ARRAY(SAVE, 11),
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CSR_OFF_ARRAY(SAVE, 12),
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CSR_OFF_ARRAY(SAVE, 13),
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CSR_OFF_ARRAY(SAVE, 14),
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CSR_OFF_ARRAY(SAVE, 15),
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CSR_OFF(TID),
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CSR_OFF_FUNCS(TCFG, CSRFL_IO, NULL, gen_helper_csrwr_tcfg),
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CSR_OFF_FUNCS(TVAL, CSRFL_READONLY | CSRFL_IO, gen_helper_csrrd_tval, NULL),
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CSR_OFF(CNTC),
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CSR_OFF_FUNCS(TICLR, CSRFL_IO, NULL, gen_helper_csrwr_ticlr),
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CSR_OFF(LLBCTL),
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CSR_OFF(IMPCTL1),
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CSR_OFF(IMPCTL2),
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CSR_OFF(TLBRENTRY),
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CSR_OFF(TLBRBADV),
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CSR_OFF(TLBRERA),
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CSR_OFF(TLBRSAVE),
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CSR_OFF(TLBRELO0),
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CSR_OFF(TLBRELO1),
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CSR_OFF(TLBREHI),
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CSR_OFF(TLBRPRMD),
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CSR_OFF(MERRCTL),
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CSR_OFF(MERRINFO1),
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CSR_OFF(MERRINFO2),
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CSR_OFF(MERRENTRY),
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CSR_OFF(MERRERA),
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CSR_OFF(MERRSAVE),
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CSR_OFF(CTAG),
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CSR_OFF_ARRAY(DMW, 0),
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CSR_OFF_ARRAY(DMW, 1),
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CSR_OFF_ARRAY(DMW, 2),
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CSR_OFF_ARRAY(DMW, 3),
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CSR_OFF(DBG),
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CSR_OFF(DERA),
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CSR_OFF(DSAVE),
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};
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static bool check_plv(DisasContext *ctx)
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{
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if (ctx->base.tb->flags == MMU_USER_IDX) {
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generate_exception(ctx, EXCCODE_IPE);
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return true;
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}
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return false;
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}
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static const CSRInfo *get_csr(unsigned csr_num)
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{
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const CSRInfo *csr;
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if (csr_num >= ARRAY_SIZE(csr_info)) {
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return NULL;
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}
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csr = &csr_info[csr_num];
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if (csr->offset == 0) {
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return NULL;
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}
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return csr;
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}
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static bool check_csr_flags(DisasContext *ctx, const CSRInfo *csr, bool write)
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{
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if ((csr->flags & CSRFL_READONLY) && write) {
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return false;
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}
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if ((csr->flags & CSRFL_IO) &&
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(tb_cflags(ctx->base.tb) & CF_USE_ICOUNT)) {
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gen_io_start();
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ctx->base.is_jmp = DISAS_EXIT_UPDATE;
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} else if ((csr->flags & CSRFL_EXITTB) && write) {
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ctx->base.is_jmp = DISAS_EXIT_UPDATE;
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}
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return true;
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}
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static bool trans_csrrd(DisasContext *ctx, arg_csrrd *a)
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{
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TCGv dest;
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const CSRInfo *csr;
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if (check_plv(ctx)) {
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return false;
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}
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csr = get_csr(a->csr);
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if (csr == NULL) {
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/* CSR is undefined: read as 0. */
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dest = tcg_constant_tl(0);
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} else {
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check_csr_flags(ctx, csr, false);
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dest = gpr_dst(ctx, a->rd, EXT_NONE);
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if (csr->readfn) {
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csr->readfn(dest, cpu_env);
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} else {
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tcg_gen_ld_tl(dest, cpu_env, csr->offset);
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}
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}
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool trans_csrwr(DisasContext *ctx, arg_csrwr *a)
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{
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TCGv dest, src1;
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const CSRInfo *csr;
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if (check_plv(ctx)) {
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return false;
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}
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csr = get_csr(a->csr);
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if (csr == NULL) {
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/* CSR is undefined: write ignored, read old_value as 0. */
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gen_set_gpr(a->rd, tcg_constant_tl(0), EXT_NONE);
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return true;
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}
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if (!check_csr_flags(ctx, csr, true)) {
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/* CSR is readonly: trap. */
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return false;
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}
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src1 = gpr_src(ctx, a->rd, EXT_NONE);
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if (csr->writefn) {
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dest = gpr_dst(ctx, a->rd, EXT_NONE);
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csr->writefn(dest, cpu_env, src1);
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} else {
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dest = temp_new(ctx);
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tcg_gen_ld_tl(dest, cpu_env, csr->offset);
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tcg_gen_st_tl(src1, cpu_env, csr->offset);
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}
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gen_set_gpr(a->rd, dest, EXT_NONE);
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return true;
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}
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static bool trans_csrxchg(DisasContext *ctx, arg_csrxchg *a)
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{
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TCGv src1, mask, oldv, newv, temp;
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const CSRInfo *csr;
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if (check_plv(ctx)) {
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return false;
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}
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csr = get_csr(a->csr);
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if (csr == NULL) {
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/* CSR is undefined: write ignored, read old_value as 0. */
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gen_set_gpr(a->rd, tcg_constant_tl(0), EXT_NONE);
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return true;
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}
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if (!check_csr_flags(ctx, csr, true)) {
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/* CSR is readonly: trap. */
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return false;
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}
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/* So far only readonly csrs have readfn. */
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assert(csr->readfn == NULL);
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src1 = gpr_src(ctx, a->rd, EXT_NONE);
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mask = gpr_src(ctx, a->rj, EXT_NONE);
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oldv = tcg_temp_new();
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newv = tcg_temp_new();
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temp = tcg_temp_new();
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tcg_gen_ld_tl(oldv, cpu_env, csr->offset);
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tcg_gen_and_tl(newv, src1, mask);
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tcg_gen_andc_tl(temp, oldv, mask);
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tcg_gen_or_tl(newv, newv, temp);
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if (csr->writefn) {
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csr->writefn(oldv, cpu_env, newv);
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} else {
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tcg_gen_st_tl(newv, cpu_env, csr->offset);
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}
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gen_set_gpr(a->rd, oldv, EXT_NONE);
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tcg_temp_free(temp);
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tcg_temp_free(newv);
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tcg_temp_free(oldv);
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return true;
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}
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static bool gen_iocsrrd(DisasContext *ctx, arg_rr *a,
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void (*func)(TCGv, TCGv_ptr, TCGv))
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{
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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if (check_plv(ctx)) {
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return false;
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}
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func(dest, cpu_env, src1);
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return true;
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}
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static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a,
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void (*func)(TCGv_ptr, TCGv, TCGv))
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{
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TCGv val = gpr_src(ctx, a->rd, EXT_NONE);
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TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
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if (check_plv(ctx)) {
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return false;
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}
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func(cpu_env, addr, val);
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return true;
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}
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TRANS(iocsrrd_b, gen_iocsrrd, gen_helper_iocsrrd_b)
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TRANS(iocsrrd_h, gen_iocsrrd, gen_helper_iocsrrd_h)
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TRANS(iocsrrd_w, gen_iocsrrd, gen_helper_iocsrrd_w)
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TRANS(iocsrrd_d, gen_iocsrrd, gen_helper_iocsrrd_d)
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TRANS(iocsrwr_b, gen_iocsrwr, gen_helper_iocsrwr_b)
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TRANS(iocsrwr_h, gen_iocsrwr, gen_helper_iocsrwr_h)
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TRANS(iocsrwr_w, gen_iocsrwr, gen_helper_iocsrwr_w)
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TRANS(iocsrwr_d, gen_iocsrwr, gen_helper_iocsrwr_d)
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static void check_mmu_idx(DisasContext *ctx)
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{
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if (ctx->mem_idx != MMU_DA_IDX) {
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tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
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ctx->base.is_jmp = DISAS_EXIT;
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}
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}
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static bool trans_tlbsrch(DisasContext *ctx, arg_tlbsrch *a)
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{
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_tlbsrch(cpu_env);
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return true;
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}
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static bool trans_tlbrd(DisasContext *ctx, arg_tlbrd *a)
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{
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_tlbrd(cpu_env);
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return true;
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}
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static bool trans_tlbwr(DisasContext *ctx, arg_tlbwr *a)
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{
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_tlbwr(cpu_env);
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check_mmu_idx(ctx);
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return true;
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}
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static bool trans_tlbfill(DisasContext *ctx, arg_tlbfill *a)
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{
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_tlbfill(cpu_env);
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check_mmu_idx(ctx);
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return true;
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}
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static bool trans_tlbclr(DisasContext *ctx, arg_tlbclr *a)
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{
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_tlbclr(cpu_env);
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check_mmu_idx(ctx);
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return true;
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}
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static bool trans_tlbflush(DisasContext *ctx, arg_tlbflush *a)
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{
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_tlbflush(cpu_env);
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check_mmu_idx(ctx);
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return true;
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}
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static bool trans_invtlb(DisasContext *ctx, arg_invtlb *a)
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{
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TCGv rj = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv rk = gpr_src(ctx, a->rk, EXT_NONE);
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if (check_plv(ctx)) {
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return false;
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}
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switch (a->imm) {
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case 0:
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case 1:
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gen_helper_invtlb_all(cpu_env);
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break;
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case 2:
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gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(1));
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break;
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case 3:
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gen_helper_invtlb_all_g(cpu_env, tcg_constant_i32(0));
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break;
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case 4:
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gen_helper_invtlb_all_asid(cpu_env, rj);
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break;
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case 5:
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gen_helper_invtlb_page_asid(cpu_env, rj, rk);
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break;
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case 6:
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gen_helper_invtlb_page_asid_or_g(cpu_env, rj, rk);
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break;
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default:
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return false;
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}
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ctx->base.is_jmp = DISAS_STOP;
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return true;
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}
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static bool trans_cacop(DisasContext *ctx, arg_cacop *a)
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{
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/* Treat the cacop as a nop */
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if (check_plv(ctx)) {
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return false;
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}
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return true;
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}
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static bool trans_ldpte(DisasContext *ctx, arg_ldpte *a)
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{
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TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx);
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TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_ldpte(cpu_env, src1, tcg_constant_tl(a->imm), mem_idx);
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return true;
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}
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static bool trans_lddir(DisasContext *ctx, arg_lddir *a)
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{
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TCGv_i32 mem_idx = tcg_constant_i32(ctx->mem_idx);
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TCGv src = gpr_src(ctx, a->rj, EXT_NONE);
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TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_lddir(dest, cpu_env, src, tcg_constant_tl(a->imm), mem_idx);
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return true;
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}
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static bool trans_ertn(DisasContext *ctx, arg_ertn *a)
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{
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if (check_plv(ctx)) {
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return false;
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}
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gen_helper_ertn(cpu_env);
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ctx->base.is_jmp = DISAS_EXIT;
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return true;
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}
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static bool trans_dbcl(DisasContext *ctx, arg_dbcl *a)
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|
{
|
|
if (check_plv(ctx)) {
|
|
return false;
|
|
}
|
|
generate_exception(ctx, EXCCODE_DBP);
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|
return true;
|
|
}
|
|
|
|
static bool trans_idle(DisasContext *ctx, arg_idle *a)
|
|
{
|
|
if (check_plv(ctx)) {
|
|
return false;
|
|
}
|
|
|
|
tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next + 4);
|
|
gen_helper_idle(cpu_env);
|
|
ctx->base.is_jmp = DISAS_NORETURN;
|
|
return true;
|
|
}
|
|
#endif
|