f80872e21c
Version 2.06 of the Power architecture describes an additional page protection mechanism. Each virtual page has a "class" (0-31) recorded in the PTE. The AMR register contains bits which can prohibit reads and/or writes on a class by class basis. Interestingly, the AMR is userspace readable and writable, however user mode writes are masked by the contents of the UAMOR which is privileged. This patch implements this protection mechanism, along with the AMR and UAMOR SPRs. The architecture also specifies a hypervisor-privileged AMOR register which masks user and supervisor writes to the AMR and UAMOR. We leave this out for now, since we don't at present model hypervisor mode correctly in any case. Signed-off-by: David Gibson <david@gibson.dropbear.id.au> [agraf: fix 32-bit hosts] Signed-off-by: Alexander Graf <agraf@suse.de>
125 lines
4.5 KiB
C
125 lines
4.5 KiB
C
#if !defined (__MMU_HASH64_H__)
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#define __MMU_HASH64_H__
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#ifndef CONFIG_USER_ONLY
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#ifdef TARGET_PPC64
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void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
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int ppc_store_slb (CPUPPCState *env, target_ulong rb, target_ulong rs);
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hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr);
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int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
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int mmu_idx);
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#endif
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/*
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* SLB definitions
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*/
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/* Bits in the SLB ESID word */
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#define SLB_ESID_ESID 0xFFFFFFFFF0000000ULL
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#define SLB_ESID_V 0x0000000008000000ULL /* valid */
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/* Bits in the SLB VSID word */
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#define SLB_VSID_SHIFT 12
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#define SLB_VSID_SHIFT_1T 24
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#define SLB_VSID_SSIZE_SHIFT 62
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#define SLB_VSID_B 0xc000000000000000ULL
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#define SLB_VSID_B_256M 0x0000000000000000ULL
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#define SLB_VSID_B_1T 0x4000000000000000ULL
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#define SLB_VSID_VSID 0x3FFFFFFFFFFFF000ULL
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#define SLB_VSID_PTEM (SLB_VSID_B | SLB_VSID_VSID)
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#define SLB_VSID_KS 0x0000000000000800ULL
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#define SLB_VSID_KP 0x0000000000000400ULL
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#define SLB_VSID_N 0x0000000000000200ULL /* no-execute */
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#define SLB_VSID_L 0x0000000000000100ULL
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#define SLB_VSID_C 0x0000000000000080ULL /* class */
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#define SLB_VSID_LP 0x0000000000000030ULL
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#define SLB_VSID_ATTR 0x0000000000000FFFULL
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/*
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* Hash page table definitions
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*/
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#define HPTES_PER_GROUP 8
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#define HASH_PTE_SIZE_64 16
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#define HASH_PTEG_SIZE_64 (HASH_PTE_SIZE_64 * HPTES_PER_GROUP)
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#define HPTE64_V_SSIZE_SHIFT 62
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#define HPTE64_V_AVPN_SHIFT 7
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#define HPTE64_V_AVPN 0x3fffffffffffff80ULL
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#define HPTE64_V_AVPN_VAL(x) (((x) & HPTE64_V_AVPN) >> HPTE64_V_AVPN_SHIFT)
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#define HPTE64_V_COMPARE(x, y) (!(((x) ^ (y)) & 0xffffffffffffff80ULL))
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#define HPTE64_V_LARGE 0x0000000000000004ULL
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#define HPTE64_V_SECONDARY 0x0000000000000002ULL
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#define HPTE64_V_VALID 0x0000000000000001ULL
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#define HPTE64_R_PP0 0x8000000000000000ULL
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#define HPTE64_R_TS 0x4000000000000000ULL
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#define HPTE64_R_KEY_HI 0x3000000000000000ULL
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#define HPTE64_R_RPN_SHIFT 12
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#define HPTE64_R_RPN 0x0ffffffffffff000ULL
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#define HPTE64_R_FLAGS 0x00000000000003ffULL
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#define HPTE64_R_PP 0x0000000000000003ULL
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#define HPTE64_R_N 0x0000000000000004ULL
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#define HPTE64_R_G 0x0000000000000008ULL
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#define HPTE64_R_M 0x0000000000000010ULL
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#define HPTE64_R_I 0x0000000000000020ULL
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#define HPTE64_R_W 0x0000000000000040ULL
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#define HPTE64_R_WIMG 0x0000000000000078ULL
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#define HPTE64_R_C 0x0000000000000080ULL
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#define HPTE64_R_R 0x0000000000000100ULL
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#define HPTE64_R_KEY_LO 0x0000000000000e00ULL
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#define HPTE64_R_KEY(x) ((((x) & HPTE64_R_KEY_HI) >> 60) | \
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(((x) & HPTE64_R_KEY_LO) >> 9))
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#define HPTE64_V_1TB_SEG 0x4000000000000000ULL
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#define HPTE64_V_VRMA_MASK 0x4001ffffff000000ULL
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static inline target_ulong ppc_hash64_load_hpte0(CPUPPCState *env,
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hwaddr pte_offset)
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{
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if (env->external_htab) {
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return ldq_p(env->external_htab + pte_offset);
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} else {
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return ldq_phys(env->htab_base + pte_offset);
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}
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}
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static inline target_ulong ppc_hash64_load_hpte1(CPUPPCState *env,
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hwaddr pte_offset)
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{
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if (env->external_htab) {
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return ldq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2);
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} else {
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return ldq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2);
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}
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}
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static inline void ppc_hash64_store_hpte0(CPUPPCState *env,
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hwaddr pte_offset, target_ulong pte0)
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{
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if (env->external_htab) {
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stq_p(env->external_htab + pte_offset, pte0);
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} else {
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stq_phys(env->htab_base + pte_offset, pte0);
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}
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}
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static inline void ppc_hash64_store_hpte1(CPUPPCState *env,
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hwaddr pte_offset, target_ulong pte1)
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{
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if (env->external_htab) {
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stq_p(env->external_htab + pte_offset + HASH_PTE_SIZE_64/2, pte1);
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} else {
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stq_phys(env->htab_base + pte_offset + HASH_PTE_SIZE_64/2, pte1);
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}
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}
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typedef struct {
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uint64_t pte0, pte1;
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} ppc_hash_pte64_t;
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#endif /* CONFIG_USER_ONLY */
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#endif /* !defined (__MMU_HASH64_H__) */
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