119df56bf0
Aspeed 2600 SDK enables I3C support by default. The I3C driver will try to reset the device controller and set it up through device address table register. This dummy model responds to these registers with default values as listed in the ast2600v10 datasheet chapter 54.2. This avoids a guest machine kernel panic due to referencing an invalid kernel address if the device address table register isn't set correctly. Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> Message-id: 20220111084546.4145785-2-troy_lee@aspeedtech.com [PMM: tidied commit message; fixed format strings] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
49 lines
1.1 KiB
C
49 lines
1.1 KiB
C
/*
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* ASPEED I3C Controller
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*
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* Copyright (C) 2021 ASPEED Technology Inc.
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*
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* This code is licensed under the GPL version 2 or later. See
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* the COPYING file in the top-level directory.
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*/
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#ifndef ASPEED_I3C_H
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#define ASPEED_I3C_H
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#include "hw/sysbus.h"
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#define TYPE_ASPEED_I3C "aspeed.i3c"
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#define TYPE_ASPEED_I3C_DEVICE "aspeed.i3c.device"
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OBJECT_DECLARE_TYPE(AspeedI3CState, AspeedI3CClass, ASPEED_I3C)
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#define ASPEED_I3C_NR_REGS (0x70 >> 2)
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#define ASPEED_I3C_DEVICE_NR_REGS (0x300 >> 2)
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#define ASPEED_I3C_NR_DEVICES 6
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OBJECT_DECLARE_SIMPLE_TYPE(AspeedI3CDevice, ASPEED_I3C_DEVICE)
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typedef struct AspeedI3CDevice {
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/* <private> */
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SysBusDevice parent;
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/* <public> */
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MemoryRegion mr;
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qemu_irq irq;
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uint8_t id;
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uint32_t regs[ASPEED_I3C_DEVICE_NR_REGS];
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} AspeedI3CDevice;
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typedef struct AspeedI3CState {
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/* <private> */
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SysBusDevice parent;
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/* <public> */
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MemoryRegion iomem;
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MemoryRegion iomem_container;
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qemu_irq irq;
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uint32_t regs[ASPEED_I3C_NR_REGS];
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AspeedI3CDevice devices[ASPEED_I3C_NR_DEVICES];
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} AspeedI3CState;
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#endif /* ASPEED_I3C_H */
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