Max Filippov 2c09eee112 target-xtensa: add basic tests for cache opcodes ...

Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>

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..

crt.S

tests: mv tests/* -> tests/tcg

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linker.ld

tests: mv tests/* -> tests/tcg

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macros.inc

target-xtensa: allow using core configuration in tests

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Makefile

target-xtensa: add basic tests for cache opcodes

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test_b.S

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test_bi.S

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test_boolean.S

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test_break.S

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test_bz.S

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test_cache.S

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test_clamps.S

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test_extui.S

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test_fail.S

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test_interrupt.S

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test_loop.S

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test_mac16.S

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test_max.S

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test_min.S

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test_mmu.S

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test_mul16.S

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test_mul32.S

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test_nsa.S

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test_pipeline.S

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test_quo.S

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test_rem.S

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test_rst0.S

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test_s32c1i.S

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test_sar.S

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test_sext.S

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test_shift.S

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test_sr.S

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test_timer.S

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test_windowed.S

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vectors.S

tests: mv tests/* -> tests/tcg

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