qemu-e2k/target/riscv
Richard Henderson fa947a667f hw/core: Make do_unaligned_access noreturn
While we may have had some thought of allowing system-mode
to return from this hook, we have no guests that require this.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2021-09-21 19:36:44 -07:00
..
insn_trans target/riscv: Use {get,dest}_gpr for RVV 2021-09-01 11:59:12 +10:00
arch_dump.c
bitmanip_helper.c
cpu_bits.h target/riscv: csr: Rename HCOUNTEREN_CY and friends 2021-09-21 12:10:47 +10:00
cpu_helper.c target/riscv: Backup/restore mstatus.SD bit when virtual register swapped 2021-09-21 12:10:22 +10:00
cpu_user.h
cpu-param.h
cpu.c target/riscv: Expose interrupt pending bits as GPIO lines 2021-09-21 07:56:49 +10:00
cpu.h hw/core: Make do_unaligned_access noreturn 2021-09-21 19:36:44 -07:00
csr.c target/riscv: csr: Rename HCOUNTEREN_CY and friends 2021-09-21 12:10:47 +10:00
fpu_helper.c
gdbstub.c
helper.h
insn16.decode
insn32.decode
instmap.h
internals.h
Kconfig
machine.c
meson.build
monitor.c
op_helper.c
pmp.c
pmp.h
trace-events
trace.h
translate.c accel/tcg: Add DisasContextBase argument to translator_ld* 2021-09-14 12:00:20 -07:00
vector_helper.c